View MC80F0704_137375.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0704/0708 MC80F0804/0808
User's Manual (Ver. 1.02)
www.DataSheet.in
Version 1.02 Published by FAE Team (c)2006 ABOV semiconductor Co., Ltd. All right reserved. Additional information of this manual may be served by ABOV semiconductor offices in Korea or Distributors and Representatives. ABOV semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
www.DataSheet.in
MC80F0704/0708/0804/0808
REVISION HISTORY
VERSION 1.02 (August 18, 2009) This Book Rearranged device order and fixed some errata. The figures of flash writer were updated in "1. OVERVIEW" on page 1. Config Read Voltage(VCONFIG), maximum VDD Start Voltage(VSTART) and Figure 7-1 were added in "7.4 DC Electrical Characteristics" on page 16. The recommended loadcapacitor values for main-oscillator circuit were added to 10pF~30pF in "10. CLOCK GENERATOR" on page 42. In case AVREF voltage was less than VDD voltage for ADC, the table-note and note were added in "7.3 A/D Converter Characteristics" on page 15 and "14. ANALOG TO DIGITAL CONVERTER" on page 69. VERSION 1.01 (JUN 3, 2008) Internal OSC specification was changed. VERSION 1.0 (FEB 27, 2008) Added AVREF parameter minimum voltage in "7.3 A/D Converter Characteristics" on page 15. Added charaeristics graphs in "7.6 Typical Characteristics" on page 19. VERSION 0.5 (SEP 28, 2007) Fixed error in description and diagram of 8bit event counter. VERSION 0.4 (MAY 5, 2007) Added 2.2V ~ 5.5V @ 1 ~ 4MHz in"7.2 Recommended Operating Conditions" on page 15. Fixed error in Figure 9-2 on page 37 : changed R04, R07 and EC0,EC1 of PSR1 to R05, R06 and T0O, T2O VERSION 0.3 (MAY 2, 2007) Added 28 QFNP package in "3. PIN ASSIGNMENT" on page 5. VERSION 0.21 (MAR. 2007) Changed 28 SOP package drawing in "4. PACKAGE DRAWING" on page 6. VERSION 0.2 (MAR. 2007) Added TVDD parameter specification. Note for configuration option was added and fix some errata. VERSION 0.1 (AUG. 2006) First Edition (Preliminary)
August 18, 2009 Ver 1.02
3
www.DataSheet.in
MC80F0704/0708/0804/0808
4
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Table of Contents
1. OVERVIEW .........................................................1 Description ........................................................1 Features ............................................................1 Development Tools ...........................................2 Ordering Information .......................................3 2. BLOCK DIAGRAM .............................................4 3. PIN ASSIGNMENT .............................................5 4. PACKAGE DRAWING ........................................6 5. PIN FUNCTION ...................................................9 6. PORT STRUCTURES .......................................11 7. ELECTRICAL CHARACTERISTICS ................15 Absolute Maximum Ratings ............................15 Recommended Operating Conditions .............15 A/D Converter Characteristics ........................15 DC Electrical Characteristics ..........................16 AC Characteristics ..........................................17 Typical Characteristics ....................................19 8. MEMORY ORGANIZATION .............................23 Registers .........................................................23 Program Memory ............................................26 Data Memory ..................................................28 Addressing Mode ............................................33 9. I/O PORTS ........................................................37 R0 and R0IO register ......................................37 R1 and R1IO register ......................................38 R2 and R2IO register ......................................40 R3 and R3IO register ......................................41 10. CLOCK GENERATOR ...................................42 Oscillation Circuit ...........................................42 11. BASIC INTERVAL TIMER ..............................44 12. WATCHDOG TIMER ......................................46 13. TIMER/EVENT COUNTER .............................49 8-bit Timer / Counter Mode ............................ 52 16-bit Timer / Counter Mode .......................... 57 8-bit Compare Output (16-bit) ........................ 58 8-bit Capture Mode ........................................ 58 16-bit Capture Mode ...................................... 63 PWM Mode .................................................... 65 14. ANALOG TO DIGITAL CONVERTER ........... 69 15. SERIAL INPUT/OUTPUT (SIO) ..................... 72 Transmission/Receiving Timing ..................... 73 The usage of Serial I/O .................................. 75 16. BUZZER FUNCTION ..................................... 76 17. INTERRUPTS ................................................ 78 Interrupt Sequence ......................................... 81 BRK Interrupt ................................................. 82 Multi Interrupt ................................................. 82 External Interrupt ............................................ 84 18. POWER SAVING OPERATION ..................... 86 Sleep Mode .................................................... 86 Stop Mode ...................................................... 87 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode .................................................... 90 Minimizing Current Consumption ................... 92 19. RESET ........................................................... 94 20. POWER FAIL PROCESSOR ......................... 96 21. COUNTERMEASURE OF NOISE ................. 98 Oscillation Noise Protector ............................. 98 Oscillation Fail Processor ............................... 99 22. Device Configuration Area ........................ 100 23. Emulator EVA. Board Setting .................. 101 A. INSTRUCTION .................................................. ii Terminology List .................................................ii Instruction Map .................................................. iii Instruction Set ...................................................iv
August 18, 2009 Ver 1.02
1
www.DataSheet.in
MC80F0704/0708/0804/0808
2
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
MC80F0704/0708 MC80F0804/0808
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 10-BIT A/D CONVERTER
1. OVERVIEW
1.1 Description
The MC80F0704/0708/0804/0808 is advanced CMOS 8-bit microcontroller with 4K/8K bytes of FLASH(MTP). This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 8K bytes of FLASH, 256 bytes of RAM, 8/16-bit timer/counter, watchdog timer, 10-bit A/D converter, 8-bit Serial Input/ Output, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has ONP, noise filter, PFD for improving noise immunity. In addition, the MC80F0704/0708/0804/0808 supports power saving modes to reduce power consumption. This document explains the base MC80F0808, the other's eliminated functions are same as below table. Device Name MC80F0704G/0708G MC80F0704D/0708D MC80F0704U/0708U MC80F0804K/0808K MC80F0804D/0808D 4K/8K 256B 16 channel 30 port 26 port FLASH Size RAM ADC I/O PORT Package 28 SKDIP 28 SOP 28 QFN 32 SDIP 32 SOP
1.2 Features
* 8K/4K Bytes On-chip Code FLASH (MTP) * FLASH Memory - Endurance : 100 cycles - Data retention time : 10 years * 256 Bytes On-chip Data RAM (Included stack memory) * Minimum Instruction Execution Time: - 333ns at 12MHz (NOP instruction) * Programmable I/O pins (LED direct driving can be a source and sink) - MC80F0804/0808 : 29/30 - MC80F0704/0708 : 25/26 * One 8-bit Basic Interval Timer * Four 8-bit Timer/counters (or two 16-bit Timer/counter) * One Watchdog timer * One 8-bit Serial Communication Interface: - One Serial Input/Output (SIO) * Two 10-bit High Speed PWM Outputs * 10-bit A/D converter : 16 channels * One Buzzer Driving port - 488Hz ~ 250kHz@4MHz * Four External Interrupt input ports * On-chip POR (Power on Reset) * Twelve Interrupt sources - External input : 4 - Timer : 6 - A/D Conversion : 1 - SIO : 1 * Built in Noise Immunity Circuit - Noise filter - PFD (Power fail detector) - ONP (Oscillation Noise Protector) * Power Down Mode - Stop mode - Sleep mode - Internal RC-Oscillated watchdog timer mode * Operating Voltage & Frequency - 2.2V ~ 5.5V (at 1 ~ 4MHz) - 2.7V ~ 5.5V (at 1 ~ 6MHz) - 3.0V ~ 5.5V (at 1 ~ 8MHz) - 4.5V ~ 5.5V (at 1 ~ 12MHz)
August 18, 2009 Ver 1.02
1
www.DataSheet.in
MC80F0704/0708/0804/0808
* Operating Temperature : -40C ~ 85C * Oscillator Type - Crystal - Ceramic resonator - External RC Oscillator (C can be omitted)
- Internal Oscillator (4MHz/2MHz) * Package - 28SKDIP, 28SOP, 28QFN, 32SKDIP, 32SDIP - Available Pb free package
1.3 Development Tools
The MC80F0704/0708/0804/0808 is supported by a full-featured macro assembler, HMS800 C compiler, an in-circuit emulator CHOICE-Dr.TM and OTP/FLASH programmers. There are two different type of programmers such as single type and gang type. Macro assembler operates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of ABOV semiconductor. - MS-Windows based assembler - MS-Windows based Debugger - HMS800 C compiler - CHOICE-Dr. - CHOICE-Dr. EVA80C0x B/D - PGM Plus USB (Single writer) - Stand Alone GANG4 USB (Gang writer) - CHOICE - SIGMA II(Single writer) Figure 1-2 Choice-Dr. (Emulator, USB Interface)
Software Hardware (Emulator) FLASH Writer
Figure 1-1 PGM plus USB (Single Writer)
Figure 1-3 Stand Alone Gang4 USB (Gang Writer)
2
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
1.4 Ordering Information
Device name MC80F0704G MC80F0704D MC80F0704U MC80F0804K MC80F0804D MC80F0708G MC80F0708D MC80F0708U MC80F0808K MC80F0808D Pb free package: The "P" Suffix will be added at the original part number. FLASH ROM RAM Package 28SKDIP 28SOP 28QFN 32SDIP 32SOP 28SKDIP 28SOP 28QFN 32SDIP 32SOP
4K bytes
256 bytes
8K bytes
256 bytes
For example; MC80F0708G(Normal package), MC80F0708G P (Pb free package)
August 18, 2009 Ver 1.02
3
www.DataSheet.in
MC80F0704/0708/0804/0808
2. BLOCK DIAGRAM
PSW
ALU
Accumulator
Stack Pointer Data Memory
PC
RESET
System controller System Clock Controller Timing generator Clock Generator 8-bit Basic Interval Timer Interrupt Controller
Program Memory Data Table
Instruction Decoder Watch-dog Timer SIO 10-bit A/D Converter 8-bit Timer/ Counter High Speed PWM Buzzer Driver
VDD VSS Power Supply R31 / AN14 R32 / AN15 XIN / R33 XOUT / R34 R3
R0
R1
R2
R00 / INT3 / SCK R01 / AN1 / SI R02 / AN2 / SOUT R03 / AN3 / INT2 R04 / AN4 / EC0 R05 / AN5 / T0O R06 / AN6 / T2O R07 / AN7 / EC1
R10 / AN0 / Avref / PWM1O R11 / INT0 / PWM3O R12 / INT1 / BUZO R13 R14 R15 R16 R17 / AN8
R20 R21 R22 R23 / AN9 R24 / AN10 R25 / AN11 R26 / AN12 R27
4
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
3. PIN ASSIGNMENT
32SDIP/SOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
28 SKDIP/ SOP
R03 / AN3 / INT2 R02 / AN2 / SOUT R01 / AN1 / SI R00 / INT3 / SCK VSS RESET / R35 XOUT / R34 XIN / R33 R32 / AN15 R31 / AN14 R30 / AN13 R27 R26 / AN12 R25 / AN11 R24 / AN10 R23 / AN9 R04 / AN4 / EC0 R05 / AN5 / T0O R06 / AN6 / T2O R07 / AN7 / EC1 VDD R10 / AN0 / AVREF / PWM1O R11 / INT0 / PWM3O R12 / INT1 / BUZO R13 R14 R15 R16 R17 / AN8 R23 / AN9
R04/AN4 / EC0 R05 / AN5 / T0O R06 / AN6 / T2O R07 / AN7 / EC1 VDD R10 / AN0 / AVREF / PWM1O R11 / INT0 / PWM3O R12 / INT1 / BUZO R13 R14 R15 R16 R17 / AN8 R20 R21 R22
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R03 / AN3 / INT2 R02 / AN2 / SOUT R01 / AN1 / SI R00 / INT3 / SCK VSS RESET / R35 XOUT / R34 XIN / R33 R32 / AN15 R31 / AN14 R30 / AN13 R26 / AN12 R25 / AN11 R24 / AN10
XOUT / R34
R32 / AN15
R31 / AN14
17
16
21
20
19
R00 / INT3 / SCK R01 / AN1 / SI R02 / AN2 / SOUT R03 / AN3 / INT2 R04 / AN4 / EC0 R05 / AN5 / T0O R06 / AN6 / T2O
22 23 24 25 26 27 28 2 3 4 5 6 1
18
15 14 13 12 11 10 9 8 7
R30 / AN13
VSS
XIN / R33
28 QFN
RESET / R35
R26 / AN12 R25 / AN11 R24 / AN10 R23 / AN9 R17 / AN8 R16 R15
R07 / AN7 / EC1
VDD
R10 / AN0 / AVREF / PWM1O
R13
R11 / INT0 / PWM3O
August 18, 2009 Ver 1.02
R12 / INT1 / BUZO
R14
5
www.DataSheet.in
MC80F0704/0708/0804/0808
4. PACKAGE DRAWING
28 SKINNY DIP
unit: inch MAX MIN
0.314 1.389 1.381 TYP 0.170 TYP 0.130 0.306 0.292 0.284
0.022 0.014 0.067 0.059 TYP 0.100
0.349 0.341
28 SOP
unit: millimetres MAX MIN
10.60 9.80
7.90 18.00 17.55
(STAND OFF)
0.05 MIN
7.30
2.80 MAX
0.55 0.35
0.20 0.13
9.50 8.90
TYP 1.27
0.70 0.30
6
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
32 SDIP
unit: millimeter MAX MIN
TYP 10.16 29.60 MIN 0.515 29.20 9.30 8.90
4.00 3.60
3.60
3.00
0.55 0.35 1.10 0.90 TYP 1.778 0 ~ 15
4 0.35 204 0.
32 SOP
unit: millimeter MAX MIN
10.60 10.20 TYP 0.40 7.55 21.30 21.20 7.45
0.20 MIN
2.55 2.35
0.45 0.35
TYP 1.27
0.95 0.55
0 ~ 8
August 18, 2009 Ver 1.02
7
www.DataSheet.in
MC80F0704/0708/0804/0808
28 QFN
unit: millimetres MAX MIN
Top View
5.10 4.90
Bottom View
0.550 0.450 N22 N28
N1
3.250
3.050 3.250 3.050
5.10
4.90
N15
N8 0.050 0 0.050 0 0.300 0.180 A
MIN. NORM. MAX. A 0.700 0.800 0.750 0.850 0.800 0.900
Side View
8
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit, CMOS, bidirectional I/O port. R0 pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(R0IO). Port pin R00 R01 R02 R03 R04 R05 R06 R07 Alternate function INT3 ( External Interrupt Input Port3 ) SCK ( SPI CLK ) AN1 ( Analog Input Port 1 ) SI (SPI Serial Data Input ) AN2 ( Analog Input Port 2 ) SOUT ( SPI Serial Data Output ) AN3 ( Analog Input Port 3 ) INT2 ( External Interrupt Input Port2 ) AN4 ( Analog Input Port 4 ) EC0 ( Event Counter Input Source 0 ) AN5 ( Analog Input Port 5 ) T0O (Timer0 Clock Output ) AN6 ( Analog Input Port 6 ) T2O (Timer2 Clock Output ) AN7 ( Analog Input Port 7 ) EC1 ( Event Counter Input Source 1 ) Table 5-1 R0 Port In addition, R0 serves the functions of the various special features in Table 5-1 . R10~R17: R1 is an 8-bit, CMOS, bidirectional I/O port. R1 pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register (R1IO). R1 serves the functions of the various following special features in Table 5-2 Port pin R10 Alternate function AN0 ( Analog Input Port 0 ) AVref ( External Analog Reference Pin ) PWM1O ( PWM1 Output ) INT0 ( External Interrupt Input Port 0 ) PWM3O ( PWM3 Output ) INT1 ( External Interrupt Input Port 1 ) BUZ ( Buzzer Driving Output Port ) AN8 ( Analog Input Port 8 ) Table 5-2 R1 Port R20~R27 : R2 is an 8-bit, CMOS, bidirectional I/O port. R2 pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(R2IO) In addition, R2 serves the functions of the various special features in Table 5-3 . Port pin R20 R21 R22 R23 R24 R25 R26 R27 Alternate function AN9 ( Analog Input Port 9 ) AN10 ( Analog Input Port 10 ) AN11 ( Analog Input Port 11 ) AN12 ( Analog Input Port 12 ) Table 5-3 R2 Port R31~R35: R3 is a 6-bit, CMOS, bidirectional I/O port. R3 pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register (R3IO). R3 serves the functions of the serial interface following special features in Table 5-4 . Port pin R30 R31 R32 R33 R34 R35 Alternate function AN13 ( Analog Input Port 13) AN14 ( Analog Input Port 14 ) AN15 ( Analog Input Port 15 ) XIN ( Oscillation Input ) XOUT ( Oscillation Output ) RESETB ( Reset input port ) Table 5-4 R3 Port
R11 R12 R13 R14 R15 R16 R17
August 18, 2009 Ver 1.02
9
www.DataSheet.in
MC80F0704/0708/0804/0808
Pin No. PIN NAME
VDD VSS RESET (R35) XIN (R33) XOUT (R34) R00 (INT3/SCK) R01 (AN1/SI) R02 (AN2/SOUT) R03 (AN3/INT2) R04 (AN4/EC0) R05 (AN5/T0O) R06 (AN6/T2O) R07 (AN7/EC1) R10 (AN0/AVref/ PWM1O) R11 (INT0/PWM3O) R12 (INT1/BUZO) R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 R26 R27 R30(AN13) R31 (AN14) R32 (AN15)
Function In/Out
I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
32
5 28 27 25 26 29 30 31 32 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
28
5 24 23 21 22 25 26 27 28 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
28 QFN
2 21 20 18 19 22 23 24 25 26 27 28 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
First
Second
Supply voltage Circuit ground
Third
Forth
Reset signal input Oscillation Input Oscillation Output
Input only port Normal I/O Port Normal I/O Port
External Interrupt 3 Analog Input Port 1 Analog Input Port 2 Analog Input Port 3 Analog Input Port 4 Analog Input Port 5 Analog Input Port 6 Analog Input Port 7 Analog Input Port 0 External Interrupt 0 External Interrupt 1 -
SPI clock Input SPI Data Input SPI Data Output External Interrupt2 Event Counter Timer0 Output Timer2 Output Event Counter Analog Reference PWM 3 output Buzzer Driving Output -
PWM 1 output -
Normal I/O Ports
Analog Input Port 8 Analog Input Port 9 Analog Input Port 10 Analog Input Port 11 Analog Input Port 12 Analog Input Port 13 Analog Input Port 14 Analog Input Port 15
Table 5-5 Pin Description
10
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
6. PORT STRUCTURES
R13~R16,R20~R22,R27
VDD Pull-up Reg. Open Drain Reg. Data Reg. Direction Reg. VSS Data Bus VSS Pin VDD Pull-up Tr. Pull-up Reg. Open Drain Reg. VDD Data Reg. Direction Reg. Data Bus MUX RD MUX RD AN[1] ADEN & ADS[3:0] (ADCM) SI SI_EN (SIOM) Noise Filter VSS VSS Pin VDD
R01 (AN1 / SI)
VDD Pull-up Tr.
VDD
R17,R30~R32,R23~R26(AN8 ~ AN15)
VDD Pull-up Reg. Open Drain Reg. Data Reg. Direction Reg. VSS Data Bus VSS Pin VDD Pull-up Tr.
R03 (AN3/INT2), R04 (AN4/EC0),R07 (AN7/EC1)
VDD Pull-up Reg. Open Drain Reg. Data Reg. Direction Reg. Data Bus MUX RD VSS VSS Pin VDD Pull-up Tr.
VDD
VDD
MUX RD
AN[3, 7] ADEN & ADS[3:0] (ADCM) INT2, EC1, EC0 Noise Filter
AN[15:14] ADEN & ADS[3:0] (ADCM)
INT2E (PSR0.2), EC1E (PSR0.5), EC0E (PSR0.4)
August 18, 2009 Ver 1.02
11
www.DataSheet.in
MC80F0704/0708/0804/0808
R11 (INT0 / PWM3O), R12 (INT1 / BUZO)
VDD Pull-up Reg. Open Drain Reg. Data Reg. PWM3O, BUZO PWM3OE(PSR0.7) BUZOE(PSR1.2) Direction Reg. Data Bus VSS VDD Pull-up Tr.
R00 (INT3 / SCK)
VDD Pull-up Reg. Open Drain Reg. VDD Data Reg. MUX Pin VSS VDD Pull-up Tr.
VDD
MUX Pin VSS
SCK SCKO_EN(SIOM) Direction Reg. Data Bus MUX RD VSS
MUX
RD Noise Filter
INT0,INT1 INT0E(PSR0.0) INT1E(PSR0.1)
Noise Filter
SCK SCK_EN(SIOM) INT3 INT3E(PSR0.3)
Noise Filter
R02 (AN2 / SOUT)
VDD Pull-up Reg. Open Drain Reg. Data Reg. SOUT SO_EN(SIOM) Direction Reg. Data Bus RD VSS VSS VDD Pull-up Tr.
R06 (AN6 / T2O / ACLK)
VDD Pull-up Reg. Open Drain Reg. VDD Data Reg. MUX Pin T2O T2OE(PSR1.1) Direction Reg. Data Bus MUX RD VSS VSS MUX Pin VDD Pull-up Tr.
VDD
MUX
AN[2] ADEN & ADS[3:0] (ADCM) SOUT(SI) SO_OUT_EN (SIOM) AN[6] Noise Filter ADEN & ADS[3:0] (ADCM) ACLK TPS[2:0](BRGCR[6:4])
Noise Filter
12
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
R10 (AN0 / AVREF / PWM1O)
VDD Pull-up Reg. Open Drain Reg. Data Reg. PWM1O PWM1OE(PSR0.6) Direction Reg. Data Bus RD VSS VSS VDD Pull-up Tr.
RESET
VDD VDD Pull-up Tr. VDD RD Mask only Data Bus
MUX Pin
Pull-up Reg.
MUX
Internal Reset
Pin
Reset Disable (Configuration option bit) AN[0] ADEN & ADS[3:0] (ADCM) ADC Reference Voltage Input AVREFS(PSR1.3)
VSS
VDD MUX
R05 (AN5 / T0O), R06 (AN6 / T2O)
VDD Pull-up Reg. Open Drain Reg. Data Reg. T0O, T2O T0OE(PSR1.0) T2OE(PSR1.1) VSS VSS Pin MUX Pull-up Tr.
XIN, XOUT (Crystal or Ceramic Resonator)
VDD
VDD
VDD VDD
STOP VSS VDD VDD MUX RD MAIN CLOCK
XIN
Direction Reg. Data Bus
XOUT VSS
AN[5], AN[6] ADEN & ADS[3:0] (ADCM)
August 18, 2009 Ver 1.02
13
www.DataSheet.in
MC80F0704/0708/0804/0808
XIN, XOUT (External RC or R oscillation)
R33 (XIN), R34 (XOUT)
VDD Pull-up Reg. Open Drain Reg. VDD Data Reg. Direction Reg. VSS VSS XIN / R33 VDD Pull-up Tr.
VDD
VDD
STOP VSS MAIN CLOCK VDD
XIN
Data Bus IN4MCLK IN2MCLK IN4MCLKXO IN2MCLKXO CLOCK option (Configuration option bit) IN4MCLK IN2MCLK EXRC Main Clock (to ONP Block)
MUX RD
fXIN / 4 XOUT VSS
Pull-up Reg. Open Drain Reg. Data Reg. Direction Reg.
VDD Pull-up Tr.
VDD
VDD
XOUT / R34 VSS VSS
Data Bus
MUX RD
System Clock / 4 IN4MCLKXO IN2MCLKCO EXRCXO CLOCK option (Configuration option bit)
14
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage........................................................ -0.3 to +6.0 V Storage Temperature .............................................-65 to +125 C Voltage on any pin with respect to Ground (VSS) ..........................................................................-0.3 to VDD+0.3V Maximum current out of VSS pin.....................................180 mA Maximum current into VDD pin .........................................80 mA Maximum current sunk by (IOL per I/O Pin) .....................20 mA Maximum output current sourced by (IOH per I/O Pin) ............................................................................................10 mA Maximum current (IOL) .................................................160 mA Maximum current (IOH)...................................................80 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Parameter Symbol Condition fXIN=1~12MHz fXIN=1~8MHz fXIN=1~6MHz fXIN=1~4MHz VDD=4.5~5.5V VDD=3.0~5.5V VDD=2.7~5.5V VDD=2.2~5.5V VDD =2.7~5.5V Specifications Min. 4.5 3.0 2.7 2.2 1 1 1 1 -40 Max. 5.5 5.5 5.5 5.5 12 8 6 4 85 Unit
Supply Voltage
VDD
V
Operating Frequency
fXIN
MHz
Operating Temperature
TOPR
C
7.3 A/D Converter Characteristics
(Ta = -40~85C, VSS = 0V, VDD =AVREF= 5.12V, 3.072V Parameter Resolution Overall Accuracy Non Liniearity Error Differential NON Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time Analog Input Voltage Analog Voltage Reference Conversion Current NNLE NDNLE NZOE NFSE NGE TCONV VAIN AVREF1 ICON VDD=5.12V, fXIN=8MHz fXIN=4MHz Symbol Conditions Min. 13 VSS 2.7V Typ. 10 - - - - 80 Max. 3 3 3 3 3 3 VDD (AVREF) VDD 200 Unit BIT LSB LSB LSB LSB LSB LSB S V V A
August 18, 2009 Ver 1.02
15
www.DataSheet.in
MC80F0704/0708/0804/0808
1. If the AVREF voltage is less than VDD voltage and anlalog input pins(ANX), shared with various alternate function, are used bidirectional I/O port, the leakage current may flow VDD pin to AVREF pin in output high mode or anlalog input pins(ANX) to AVREF pin in input high mode.
7.4 DC Electrical Characteristics
(TA=-40~85C, VDD=5.0V, VSS=0V), Specifications Min. 0.8 VDD 0.8 VDD 0.7 VDD 0 0 0 VDD=5V, IOH=-5mA VDD=5V, IOL=10mA VDD=5V VDD=5V VDD=5V VDD=5V VDD=5V VDD=5V VDD -1
-
Parameter
Symbol VIH1
Pin XIN, RESET Hysteresis Input1 Normal Input XIN, RESET Hysteresis Input1 Normal Input All Output Port All Output Port Normal Input All Pins (except XIN) XIN All Pins (except XIN) XIN Hysteresis Input1 VDD XOUT VDD VDD VDD VDD XOUT XOUT VDD VDD
Condition
Typ. 2.8 65 8.8 1 20 4 4 2 2.9
Max. VDD VDD VDD 0.2 VDD 0.2 VDD 0.3 VDD 1 -150 5 13 3.2 95 15 2 50 10 4.5 2.25 40 0.7 3.4
Unit
Input High Voltage
VIH2 VIH3 VIL1
V
Input Low Voltage
VIL2 VIL3
V
Output High Voltage Output Low Voltage Input Pull-up Current Input High Leakage Current Input Low Leakage Current Hysteresis PFD Voltage Internal RC WDT Period Operating Current2 Sleep Mode Current RCWDT Mode Current at STOP Mode Stop Mode Current Internal 4MHz Oscillation Frequency Internal 2MHz Oscillation Frequency VDD Rising Time VDD Start Voltage Config Read Voltage Power On Reset
VOH VOL IP IIH1 IIH2 IIL1 IIL2 | VT | VPFD TRCWDT IDD ISLEEP IRCWDT ISTOP TIN4MCLK TIN2MCLK TVDD3 VSTART3
V V A A A A A V V S mA mA A A MHz MHz ms/V V V V
-60 -5 -13 0.5 2.0
VDD=5.0V VDD=5.5V,fXIN=12MHz VDD=5.5V,fXIN=12MHz VDD=5.5V,fXIN=12MHz VDD=5.5V,fXIN=12MHz VDD=5V, 25C VDD=5V, 25C
25 3.5 1.75 VSS
VCONFIG3 VDD VPOR VDD
TVDD=40ms/V, VSTART=VSS
1.8 2.4
16
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Parameter
Symbol fRC-OSC fR-OSC
Pin fXOUT = fRC-OSC / 4 fXOUT = fR-OSC / 4
Condition VDD=5.5V R=30k, C=10pF VDD=5.5V, R=30k
Specifications Min. 0.5 1 Typ. 1.5 2 Max. 2.5 3
Unit MHz MHz
External RC Oscillator Frequency
1. Hysteresis Input: INT0 ~INT3(R11,R12,R03,R00),SIO(R00,R01,R02), EC0,EC1(R04,R07) 2. This parameter is measured in internal PROM operation at the all I/O port defined input mode. 3. These parameters are presented for design guidance only and not tested or guaranteed.
V VDD
TVDD 40ms/V
VDDMIN Config(POR) Read Detection Point VCONFIG Config(POR) Read Detection Point
No Config(POR) Read VSTART 0V
T
Figure 7-1 Config Read Voltage including POR vs Supply Voltage
7.5 AC Characteristics
(TA=-40~+85C, VDD=5V10%, VSS=0V) Specifications Min. 1 35 2 8 Typ. Max. 12 20 20 -
Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time(4MHz) External Input Pulse Width RESET Input Width
Symbol fCP tCPW tRCP,tFCP tST tEPW tRST
Pins XIN XIN XIN XIN, XOUT INT0, INT1, INT2, INT3 EC0, EC1 RESET
Unit MHz nS nS mS tSYS tSYS
August 18, 2009 Ver 1.02
17
www.DataSheet.in
MC80F0704/0708/0804/0808
1/fCP
tCPW
tCPW VDD-0.5V
XIN
tSYS tRCP tFCP
0.5V
tRST
RESET
0.2VDD
tEPW
tEPW 0.8VDD
INT0, INT1 INT2, INT3 EC0, EC1
0.2VDD
Figure 7-2 Timing Chart
18
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
7.6 Typical Characteristics
These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the
fXIN (MHz) 16 14 12 10 8 6 4 2 0 2 3 4 5 6 VDD (V) IDD (mA)
specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation.
Operating Area
Ta=25C
Normal Operation IDD-VDD
Ta=25C
12
10 8 fXIN=12MHz 6 4 2 0 2 3 4 5 VDD 6 (V) 4MHz
STOP Mode ISTOP-VDD
IDD (A) 2 1.5 1 0.5 0 2 3 4 5 VDD (V) Ta=25C IDD (mA) 2.0 1.5 1.0 0.5 0
SLEEP Mode ISLEEP-VDD
Ta=25C fXIN = 12MHz
2
3
4
5
VDD 6 (V)
RC-WDT in Stop Mode IRCWDT-VDD
IDD (A) 20 15 TRCWDT = 50uS 10 5 0 2 3 4 5 VDD 6 (V) Ta=25C
August 18, 2009 Ver 1.02
19
www.DataSheet.in
MC80F0704/0708/0804/0808
IOL-VOL, VDD=5V
IOL (mA) 20 -25C 25C 85C 15 -15 IOH (mA) -20
IOH-VOH, VDD=5V
-25C 25C 85C
10
-10
5 0 0.5 1 1.5 2 VOL (V)
-5 0 3.5 4 4.5 5 VOH (V)
VIH1 (V) 4 3 2 1 0
VDD-VIH1 XIN, RESET
fXIN=4MHz Ta=25C
VDD-VIH2
VIH2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 fXIN=4kHz Ta=25C
Hysteresis input
VDD-VIH3
VIH3 (V) 4 3 2 1 fXIN=4kHz Ta=25C
Normal input
1
2
3
4
5
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
VIL1 (V) 4 3 2 1 0
VDD-VIL1 XIN, RESET
fXIN=4MHz Ta=25C
VDD-VIL2
VIL2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 fXIN=4kHz Ta=25C
Hysteresis input
VDD-VIL3
VIL3 (V) 4 3 2 1 fXIN=4kHz Ta=25C
Normal input
1
2
3
4
5
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
20
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
FOSC (MHz) 10 9
Typical RC Oscillator Frequency vs VDD
No Cap Ta = 25C
FOSC (MHz) 10 9
Typical RC Oscillator Frequency vs VDD
CEXT = 10pF Ta = 25C
R = 4.7K 8 7 6 5 4 R = 20K 3 R = 30K 2 1 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD 5.5 (V) 2 1 0 2.5 3.0 3.5 4.0 4.5 5.0 R = 30K VDD 5.5 (V) 3 R = 20K R = 10K 8 7 6 5 4 R = 10K R = 4.7K
FOSC (MHz) 7 6
Typical RC Oscillator Frequency vs VDD
CEXT = 20pF Ta = 25C
FOSC (MHz) 7 6
Typical RC Oscillator Frequency vs VDD
CEXT = 30pF Ta = 25C
R = 4.7K 5 4 R = 10K 3 2 1 0 2.5 3.0 3.5 4.0 4.5 5.0 R = 20K 3 2 1 VDD 5.5 (V) 0 2.5 3.0 5 4
R = 4.7K
R = 10K R = 20K R = 30K 3.5 4.0 4.5 5.0 VDD 5.5 (V)
R = 30K
Note: The external RC oscillation frequencies shown in above are provided for design guidance only and not tested or guaranteed. The user needs to take into account that the external RC oscillation frequencies generated by the same circuit design may be not the same. Because there are variations in the resistance and capacitance due to the tolerance of external R and C components. The parasitic capacitance difference due to the different wiring length and layout may change the external RC oscillation frequencies.
Note: There may be the difference between package types(PDIP, SOP, TSSOP). The user should modify the value of R and C components to get the proper frequency in MC80F0704/0708/0804/0808 or one package type to another package type.
August 18, 2009 Ver 1.02
21
www.DataSheet.in
MC80F0704/0708/0804/0808
FOSC (MHz)
Typical Internal 4MHz Frequency vs VDD
Ta = 25C 5
by sample, voltage and temperature. The internal oscillation can be used only in timing insensitive application.
4.5
4
3.5 2.5 3.0 3.5 4.0 4.5 5.0
VDD 5.5 (V)
Note: The internal 4MHz oscillation frequencies shown in above are provided for design guidance only and not tested or guaranteed. The user needs to take into account that the internal oscillation of the MC80F0704/0708/0804/0808 or MC80F0808(4) may show different frequency with sample
22
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
8. MEMORY ORGANIZATION
The MC80F0704/0708/0804/0808 has separate address spaces for Program memory and Data Memory. 4K bytes program memory can only be read, not written to. Data memory can be read and written to up to 256 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Bit 15
Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 1C0H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used.
Stack Address (1C0H ~ 1FFH) 87 Bit 0 01H SP C0H~FFH Hardware fixed
Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y Y A Two 8-bit Registers can be used as a "YA" 16-bit Register A
Note: The Stack Pointer must be initialized by software because its value is undefined after Reset. Example: To initialize the SP LDX #0FFH TXSP
; SP FFH
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).
August 18, 2009 Ver 1.02
23
www.DataSheet.in
MC80F0704/0708/0804/0808
PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is selected to "page 1" BRK FLAG
MSB NVGBH
I
Z
LSB C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
24
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
At execution of a CALL/TCALL/PCALL Push down
At acceptance of interrupt
At execution of RET instruction
At execution of RET instruction
01FF 01FE 01FD 01FC
PCH PCL
01FF 01FE 01FD 01FC
PCH PCL PSW
Push down
01FF 01FE 01FD 01FC
PCH PCL
Pop up
01FF 01FE 01FD 01FC
PCH PCL PSW
Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FF 01FE 01FD 01FC A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FF 01FE 01FD 01FC 01FFH A Pop up 01C0H
Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-4 Stack Operation
August 18, 2009 Ver 1.02
25
www.DataSheet.in
MC80F0704/0708/0804/0808
8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4K/8K/16K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program Example: Usage of TCALL LDA #5 TCALL 0FH : :
C000H E000H
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORMAL CALL
1
;TCALL ADDRESS AREA
FFC0H FFDFH FFE0H FFFFH
TCALL area Interrupt Vector Area
PCALL area
4K ROM
FEFFH FF00H
8K ROM
16K ROM
F000H
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFFAH and 0FFFBH for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7 .
Address 0FFE0H E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE Vector Area Memory Basic Interval Timer Watchdog Timer Interrupt A/D Converter Timer/Counter 3 Interrupt Timer/Counter 2 Interrupt Timer/Counter 1 Interrupt Timer/Counter 0 Interrupt Serial Input/Output (SIO) External Interrupt 3 External Interrupt 2 External Interrupt 1 External Interrupt 0 RESET
Figure 8-6 Interrupt Vector Area
26
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Address 0FF00H
PCALL Area Memory
Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0.
PCALL Area (256 Bytes)
0FFFFH
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4A ~ ~ 4F 35 0D125H NEXT ~ ~ FH FH
01001010
Reverse
PC: 11111111 11010110 DH 6H
~ ~
0FF00H 0FF35H NEXT
~ ~
0FF00H 0FFD6H 0FFD7H 0FFFFH 25 D1
0FFFFH
Example: The usage software example of Vector address
August 18, 2009 Ver 1.02
27
www.DataSheet.in
MC80F0704/0708/0804/0808
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, control registers, and Stack memory.
0000H User Memory (192Bytes) 00BFH 00C0H 00FFH 0100H PAGE0 Control Registers (When "G-flag=0", this page0 is selected)
blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example "LDM". Example; To write at CKCTLR LDM CKCTLR,#0AH ;Divide ratio(/32)
Not Available 01BFH 01C0H User Memory or Stack Area (64 bytes) PAGE1
01FFH
Stack Area
Figure 8-8 Data Memory Map The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 25.
User Memory
The MC80F0704/0708/0804/0808 has 256 x 8 bits for the user memory (RAM). RAM pages are selected by RPR (See Figure 89 ). Note: After setting RPR(RAM Page Select Register), be sure to execute SETG instruction. When executing CLRG instruction, be selected PAGE0 regardless of RPR.
Control Registers
The control registers are used by the CPU and Peripheral function
R/W 2 R/W 1
7
6 -
5 -
4 -
3 -
R/W 0
RPR
-
RPR1 RPR0
ADDRESS: 0E1H INITIAL VALUE: ---- --00B System clock source select 00 : PAGE0 01 : PAGE1 others : Setting prohibited
Figure 8-9 RPR(RAM Page Select Register)
28
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Address 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00D0
Register Name R0 port data register R0 port I/O direction register R1 port data register R1 port I/O direction register R2 port data register R2 port I/O direction register R3 port data register R3 port I/O direction register Port 0 Open Drain Selection Register Port 1 Open Drain Selection Register Port 2 Open Drain Selection Register Port 3 Open Drain Selection Register Timer 0 mode control register Timer 0 register
Symbol R0 R0IO R1 R1IO R2 R2IO R3 R3IO R0OD R1OD R2OD R3OD TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR T1PWHR TM2 T2 TDR2 CDR2 TM3 TDR3 T3PPR T3 T3PDR CDR3
R/W R/W W R/W W R/W W R/W W W W W W R/W R W R R/W W W R R R/W W R/W R W R R/W W W R R/W R
Initial Value
76543210
Addressing Mode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte byte byte byte byte, bit
00000000 00000000 00000000 00000000 00000000 00000000 -000000 -000000
00000000 00000000 00000000 -000000 -000000
00000000 11111111 00000000 00000000 11111111 11111111 00000000 00000000 00000000 -0000 byte, bit byte byte byte byte bit byte, bit byte
00D1
Timer 0 data register Timer 0 capture data register
00D2 00D3
Timer 1 mode control register Timer 1 data register Timer 1 PWM period register Timer 1 register
00D4
Timer 1 capture data register Timer 1 PWM duty register
00D5 00D6
Timer 1 PWM high register Timer 2 mode control register Timer 2 register
-000000
00000000 11111111 00000000 00000000 11111111 11111111 00000000 00000000 00000000 byte byte, bit byte byte
00D7
Timer 2 data register Timer 2 capture data register
00D8 00D9
Timer 3 mode control register Timer 3 data register Timer 3 PWM period register Timer 3 register
00DA
Timer 3 PWM duty register Timer 3 capture data register
Table 8-1 Control Registers
August 18, 2009 Ver 1.02
29
www.DataSheet.in
MC80F0704/0708/0804/0808
Address 00DB 00E0 00E1 00E2 00E3 00EA 00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2
Register Name Timer 3 PWM high register Buzzer driver register RAM page selection register SIO mode control register SIO data shift register Interrupt enable register high Interrupt enable register low Interrupt request register high Interrupt request register low Interrupt edge selection register A/D converter mode control register A/D converter result high register A/D converter result low register Basic interval timer register Clock control register Watch dog timer register Watch dog timer data register Stop & sleep mode control register PFD control register Port selection register 0 Port selection register 1 Pull-up selection register 0 Pull-up selection register 1 pull-up selection register 2 Pull-up selection register 3
Symbol T3PWHR BUZR RPR SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCRH ADCRL BITR CKCTLR WDTR WDTDR SSCR PFDR PSR0 PSR1 PU0 PU1 PU2 PU3
R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R(W) R R W W R W R/W W W W W W W -
Initial Value
76543210
Addressing Mode byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte
-
-0000
11111111 -000
00000001 Undefined 00000000 00000000 00000000 00000000 00000000 00000001 010 Undefined
Undefined Undefined 0-010111 01111111 Undefined 00000000 -000
00F4 00F5 00F7 00F8 00F9 00FC 00FD 00FD 00FF
byte byte byte, bit byte byte byte byte byte byte
00000000 -0000
00000000 00000000 00000000 -000000
Table 8-1 Control Registers
1. The `byte, bit' means registers are controlled by both bit and byte manipulation instruction. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated. The `byte' means registers are controlled by only byte manipulation instruction. Do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value.
2.
*The mark of `-' means this bit location is reserved.
30
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0E0H 0E1H 0E2H 0E3H 0EAH 0EBH 0ECH 0EDH
Name R0 R0IO R1 R1IO R2 R2IO R3 R3IO R0OD R1OD R2OD R3OD TM0 T0/TDR0/ CDR0 TM1 TDR1/ T1PPR T1/CDR1 PWM1HR TM2 T2/TDR2/ CDR2 TM3 TDR3/ T3PPR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register R0 Port Direction Register R1 Port Data Register R1 Port Direction Register R2 Port Data Register R2Port Data Register R3 Port Data Register R3 Port Direction Register R0 Open Drain Selection Register R1 Open Drain Selection Register R2 Open Drain Selection Register R3 Open Drain Selection Register CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register T1_POL T1_16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST
Timer1 Data Register / Timer1 PWM Period Register Timer1 Register / Timer1 Capture Data Register -
Timer1 PWM High Register T2CK1 T2CK0 T2CN T2ST
-
CAP2
T2CK2
Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register T3_POL T3_16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST
Timer3 Data Register / Timer3 PWM Period Register
T3/CDR3/ Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register T3PDR PWM3HR BUZR RPR SIOM SIOR IENH IENL IRQH IRQL BUCK1 POL INT0E T1E INT0IF T1IF
-
Timer3 PWM High Register BUR3 SCK1 ADCE ADCIF BUR2 RPR2 SCK0 WDTE WDTIF BUR1 RPR1 SIOST SIOE WTE SIOIF WTIF BUR0 RPR0 SIOSF T0E BITE T0IF BITIF
BUCK0 IOSW INT1E T2E INT1IF T2IF
BUR5 SM1 INT2E T3E INT2IF T3IF
BUR4 SM0 INT3E INT3IF T4IF
SIO Data Shift Register
Table 8-2 Control Register Function Description
August 18, 2009 Ver 1.02
31
www.DataSheet.in
MC80F0704/0708/0804/0808
Address 0EEH 0EFH 0F0H 0F1H 0F2H
Name IEDS ADCM ADCRH ADCRL BITR1 CKCTLR1 WDTR WDTDR SSCR PFDR PSR0 PSR1 PU0 PU1 PU2 PU3
Bit 7 IED3H ADEN PSSEL1
Bit 6 IED3L ADCK PSSEL0
Bit 5 IED2H ADS3
ADC8
Bit 4 IED2L ADS2
-
Bit 3 IED1H ADS1
-
Bit 2 IED1L ADS0
-
Bit 1 IED0H ADST
Bit 0 IED0L ADSF
ADC Result Reg. High
ADC Result Register Low Basic Interval Timer Data Register ADRST WDTCL RCWDT WDTON BTCL BTS2 BTS1 BTS0
0F4H 0F5H 0F7H 0F8H 0F9H 0FCH 0FDH 0FEH 0FFH
7-bit Watchdog Timer Register
Watchdog Timer Data Register (Counter Register) Stop & Sleep Mode Control Register PWM3O PWM1O EC1E EC0E INT3E XTEN PFDEN INT2E BUZO PFDM INT1E T2O PFDS INT0E T0O
R0 Pull-up Selection Register R1 Pull-up Selection Register R2 Pull-up Selection Register R3 Pull-up Selection Register Table 8-2 Control Register Function Description
1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be accessed by register operation instruction such as "LDM dp,#imm".
32
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
8.4 Addressing Mode
The MC8 series MCU uses six addressing modes;
Direct Page Addressing dp
In this mode, a address is specified within direct page. Example; G=0 C535 LDA 35H ;A RAM[35H]
* Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
35H
data
~ ~
~ ~
Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
data A
0E550H 0E551H
C5 35
Immediate Addressing #imm
In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H
MEMORY
Absolute Addressing !abs
Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area.
A+35H+C A
04 35
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ROM[0F035H]
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1 E45535 LDM 35H,#55H
0F035H
data
~ ~
~ ~
0F100H 0F101H 0F102H data 55H 07 35 F0
A+data+C A
address: 0F035
0135H
data
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag.
August 18, 2009 Ver 1.02
33
www.DataSheet.in
MC80F0704/0708/0804/0808
983501
INC
!0135H
;A ROM[135H]
35H 135H data
data
~ ~
data A
~ ~
~ ~
DB
~ ~
0F100H 0F101H 0F102H 98 35 01

36H X
data+1 data
address: 0135
X indexed direct page (8 bit offset) dp+X Indexed Addressing X indexed direct page (no offset) {X}
In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 D4 LDA {X} ;ACCRAM[X]. This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 45H+X
3AH 115H data
data
~ ~
data A
~ ~
0E550H 0E551H C6 45
~ ~

data A
~ ~
0E550H D4
45H+0F5H=13AH
X indexed direct page, auto increment {X}+
In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+
Y indexed direct page (8 bit offset) dp+Y
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X.
Y indexed absolute !abs+Y
Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area. Example; Y=55H
34
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
D500FA
LDA
!0FA00H+Y
1625
ADC
[25H+X]
35H 0F100H 0F101H 0F102H D5 00 FA
05 E0
0FA00H+55H=0FA55H
36H
~ ~
0E005H data
~ 0E005H ~
~ ~
0FA55H data
~ ~

data A
25 + X(10) = 35H
~ ~
~ ~
0FA00H 16 25
A + data + C A Indirect Addressing Direct page indirect [dp]
Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0 3F35 JMP [35H]
Y indexed indirect [dp]+Y
Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Yregister data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H 1725 ADC [25H]+Y
35H 36H
0A E3
25H 26H
05 E0
~ ~
0E30AH NEXT
~ ~
jump to address 0E30AH
~ ~
0E015H data
~ ~
0E005H + Y(10) = 0E015H
~ ~
0FA00H 3F 35
~ ~
~ ~
0FA00H 17 25
~ ~
A + data + C A
X indexed indirect [dp+X]
Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
Absolute indirect [!abs]
The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
August 18, 2009 Ver 1.02
35
www.DataSheet.in
MC80F0704/0708/0804/0808
1F25E0
JMP
[!0C025H]
PROGRAM MEMORY
0E025H 0E026H
25 E7
~ ~
~ ~
NEXT
0E725H
jump to address 0E30AH
~ ~
0FA00H 1F 25 E0
~ ~
36
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
9. I/O PORTS
The MC80F0704/0708/0804/0808 has three ports (R0, R1 and R3). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. All port can drive maximum 20mA of high current in output low state, so it can directly drive LED device. All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1 . All the port direction registers in the MC80F0704/0708/0804/ 0808 have 0 written to them by reset function. On the other hand, its initial status is input.
WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H 0C2H 0C3H R0 data R0 direction R1 data R1 direction I O I O I O I O PORT 76543210 I: INPUT PORT O: OUTPUT PORT 01010101 76543210 BIT
Figure 9-1 Example of port I/O assignment
9.1 R0 and R0IO register
R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0IO register (address 0C1H). When R00 through R07 pins are used as input ports, an on-chip pull-up resistor can be connectR0 Data Register R0
ADDRESS: 0C0H RESET VALUE: 00H
ed to them in 1-bit units with a pull-up selection register 0 (PU0). Each I/O pin of R0 port can be used to open drain output port by setting the corresponding bit of the open drain selection register 0 (R0OD).
ADDRESS: 0F8H RESET VALUE: 0000 0000B
R07 R06 R05 R04 R03 R02 R01 R00 Input / Output data
PSR0
PWM3OE PWM1OE EC1E EC0E INT3E INT2E INT1E INT0E
R0 Direction Register R0IO
ADDRESS: 0C1H RESET VALUE: 00H
Port / INT Selection 0: R11, R12, R03, R00 1: INT0, INT1,INT2, INT3 Port / EC Selection 0: R04, R07 1: EC0, EC1
Port Direction 0: Input 1: Output
Port / PWM Selection 0: R10, R11 1: PWM1O, PWM3O
R0 Pull-up Selection Register PU0
ADDRESS: 0FCH RESET VALUE: 00H ADDRESS: 0F9H RESET VALUE: ---- 0000B Pull-up Resister Selection 0: Disable 1: Enable
PSR1
-
-
-
-
AVREFS BUZOE T2OE T0OE
R0 Open Drain Selection Register R0OD
Port / TO Selection 0: R04, R07 1: EC0, EC1 R12/BUZO Selection 0: R12 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) R10 / AVREF Selection 0: R10 port 1: AVREF port
ADDRESS: 0C8H RESET VALUE: 00H
Open Drain Resister Selection 0: Disable 1: Enable
Figure 9-2 R0 Port Register In addition, Port R0 is multiplexed with various alternate functions. The port selection register PSR0 (address 0F8H) and PSR1 (address 0F9H) control the selection of alternate functions such as external interrupt 3 (INT3), external interrupt 2 (INT2), event counter input 0 (EC0), timer 0 output (T0O), timer 2 output (T2O) and event counter input 1 (EC1). When the alternate func-
August 18, 2009 Ver 1.02
37
www.DataSheet.in
MC80F0704/0708/0804/0808
tion is selected by writing "1" in the corresponding bit of PSR0 or PSR1, port pin can be used as a corresponding alternate features regardless of the direction register R0IO. The ADC input channel 1~7 (AN1~AN7) and SIO data input (SI), SIO data output (SOUT), SIO clock input/output (SCK) can be selected by setting ADCM(00EFH) and SIOM(00E2H) register to enable the corresponding peripheral operation and select operation mode.
Port Pin R00R01 R02 R03 R04 R05 R06 R07
Alternate Function INT3 (External interrupt 3) SCK (SIO clock input/output) AN1(ADC Input channel 1) SI (SIO data input) AN2 (ADC Input channel 2) SOUT (SIO data output) AN3 (ADC Input channel 3) INT2 (External interrupt 2) AN4 (ADC Input channel 4) EC0 (Event counter input 0) AN5 (ADC Input channel 5) T0O (Timer output 0) AN6 (ADC Input channel 6) T2O (Timer output 2) AN7 (ADC Input channel 7) EC1 (Event counter input 1)
9.2 R1 and R1IO register
R1 is a 5-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1IO register (address 0C3H). When R10 through R17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 1 (PU1). Each I/O pin of R1 port can be used to open drain output port by setting the corresponding bit of the open drain selection register 1 (R1OD). In addition, Port R1 is multiplexed with various alternate functions. The port selection register PSR0 (address 0F8H) and PSR1 (address 0F9H) control the selection of alternate functions such as Analog reference voltage input (AVREF), external interrupt 0 (INT0), external interrupt 1 (INT1), PWM 1 output (PWM1O), PWM 3 output (PWM3O) and buzzer output (BUZO). When the alternate function is selected by writing "1" in the corresponding bit of PSR0 or PSR1, port pin can be used as a corresponding alternate features regardless of the direction register R1IO. The ADC input channel 0 (AN0) and channel 8(AN8) can be selected by setting ADCM(00EFH) register to enable ADC and select channel 0 and channel 8 . Port Pin R10 R11 R12 Alternate Function AN0 (ADC input channel 0) AVREF (Analog reference voltage) PWM1O (PWM 1 output) INT0 (External Interrupt 0) PWM3O (PWM 3 output) INT1 (External Interrupt 1) BUZO (Buzzer output) AN8
R13 R14 R15 R16 R17
38
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
R1 Data Register R1
ADDRESS: 0C2H RESET VALUE: 00H
ADDRESS: 0F8H RESET VALUE: 0000 0000B
R17 R16 R15 R14 R13 R12 R11 R10 Input / Output data ADDRESS: 0C3H RESET VALUE: 00H
PSR0 PWM3OEPWM1OE
EC1E EC0E INT3E INT2E INT1E INT0E
Port / INT Selection 0: R11, R12, R03, R00 1: INT0, INT1,INT2, INT3 Port / EC Selection 0: R04, R07 1: EC0, EC1 Port / PWM Selection 0: R10, R11 1: PWM1O, PWM3O
R1 Direction Register R1IO
Port Direction 0: Input 1: Output
R1 Pull-up Selection Register PU1
ADDRESS: 0FDH RESET VALUE: 00H
ADDRESS: 0F9H RESET VALUE: ---- 0000B
PSR1
Pull-up Resister Selection 0: Disable 1: Enable
-
-
-
-
AVREFS BUZOE T2OE T0OE
Port / TO Selection 0: R05, R06 1: T00, T2O R12/BUZO Selection 0: R12 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) R10 / AVREF Selection 0: R10 port 1: AVREF port
R1 Open Drain Selection Register R1OD
ADDRESS: 0C9H RESET VALUE: 00H
Open Drain Resister Selection 0: Disable 1: Enable
Figure 9-3 R1 Port Register
August 18, 2009 Ver 1.02
39
www.DataSheet.in
MC80F0704/0708/0804/0808
9.3 R2 and R2IO register
R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R3IO register (address 0C5H). When R20 through R27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 2 (PU2). R20 through R27 pins can be used to open drain output port by setting the corresponding bit of the open drain selection register 2 (R2OD). In addition, Port R2 is multiplexed with alternate functions. R23 R24,R25,and R26 can be used as ADC input channel 9 to 12 by setting ADCM to enable ADC and select channel 9 to 12. Port Pin R20 R21 R22 R23 R24 R25 R26 R27 Alternate Function AN9 (ADC input channel 9) AN10 (ADC input channel 10) AN11 (ADC input channel 11) AN12 (ADC input channel 12) Port Direction 0: Input 1: Output
R2 Data Register R2
ADDRESS: 0C4H RESET VALUE: 00H
R27 R26 R25 R24 R23 R22 R21 R20 Input / Output data
R2 Direction Register R2IO
ADDRESS: 0C5H RESET VALUE: 00H
R2 Pull-up Selection Register PU2
ADDRESS: 0FEH RESET VALUE: 00H
Pull-up Resister Selection 0: Disable 1: Enable
R2 Open Drain Selection Register R2OD
ADDRESS: 0CAH RESET VALUE: 00H
Open Drain Resister Selection 0: Disable 1: Enable
40
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
9.4 R3 and R3IO register
R3 is a 6-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin (except R35) can independently used as an input or an output through the R3IO register (address 0C7H). R35 is an input only port. When R30 through R35 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 3 (PU3). R30 through R34 pins can be used to open drain output port by setting the corresponding bit of the open drain selection register 1 (R3OD). In addition, Port R3 is multiplexed with alternate functions. R30 R31,and R32 can be used as ADC input channel 13,14 and 15 by setting ADCM to enable ADC and select channel 13,14 and 15. Port Pin R30 R31 R32 Alternate Function AN13 (ADC input channel 13) AN14 (ADC input channel 14) AN15 (ADC input channel 15)
Port Direction 0: Input 1: Output
R3 Data Register R3
-
ADDRESS: 0C6H RESET VALUE: 00H
R35 R34 R33 R32 R31 R30 Input / Output data
Input data
R3 Direction Register R3IO
-
ADDRESS: 0C7H RESET VALUE: 00H
R33, R34 and R35 is multiplexed with XIN, XOUT, and RESET pin.
R3 Pull-up Selection Register PU3
-
ADDRESS: 0FDH RESET VALUE: 00H
Pull-up Resister Selection 0: Disable 1: Enable
R3 Open Drain Selection Register R3OD
ADDRESS: 0CBH RESET VALUE: ---0 000-B
Open Drain Resister Selection 0: Disable 1: Enable
August 18, 2009 Ver 1.02
41
www.DataSheet.in
MC80F0704/0708/0804/0808
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main-frequency clock oscillator. The system clock operation can be easily obtained by attaching a crystal or a ceramic resonator between the XIN and XOUT pin, respectively. The system clock can also be obtained from the external oscillator. In this case, it is necessary to input a external clock signal to the XIN pin and open the XOUT pin. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is
STOP INOSC
Main OSC Stop INOSC
through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. To the peripheral block, the clock among the not-divided original clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided. Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock control register (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 44 for details.
SLEEP
XIN XOUT
OSC Circuit
ONP Circuit
fXIN fEX
MUX
Clock Pulse Generator (/2)
Internal system clock
Int OSC Circuit
INCLK
INOSC
PRESCALER
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
INOSC (IN4MCLK/IN2MCLK/ IN4MCLKXO/IN2MCLKXO)
7~3
2~0
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512 /1024 /2048 /4096
Configuration Option Register (20FFH)
Peripheral clock
PS1 2M 500n PS2 1M 1u PS3 500K 2u PS4 250K 4u PS5 125K 8u PS6 62.5K 16u PS7 31.25K 32u PS8 15.63K 64u PS9 7.183K 128u PS10 3.906K 256u PS11 1.953K 512u PS12 976 1.024m
fEX (Hz)
4M Frequency period
PS0 4M 250n
Figure 10-1 Block Diagram of Clock Generator
10.1 Oscillation Circuit
XIN and XOUT are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 10-2 .
C1 C2
Xout
Recommendation Crystal/Ceramic Oscillator C1,C2 = 10~30pF
Xin Vss
Cautions 1. The recommended load capacitor values(C1,C2,C3,C4) are common value but may not be appropriate for some crystal or ceramic resonator.
Figure 10-2 Oscillator Connections Note: When using a system clock oscillator, carry out wiring in
the broken line area in Figure 10-2 to prevent any effects from wir-
42
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
ing capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator.
The user needs to take into account variation due to tolerance of external R and C components used. Figure 10-1 shows how the RC combination is connected to the MC80F0704/0708/0804/0808. External capacitor (CEXT) can be omitted for more cost saving. However, the characteristics of external R only oscillation are more variable than external RC oscillation.
n addition, see Figure 10-3 for the layout of the crystal.
Vdd REXT XIN
XOUT XIN
CEXT
Cint 6pF
fXIN/4
XOUT
Figure 10-1 RC Oscillator Connections
Figure 10-3 Layout of Oscillator PCB circuit To drive the device from an external clock source, Xout should be left unconnected while Xin is driven as shown in Figure 10-4 . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
OPEN Xout
VDD REXT XIN
CINT 6pF
fXIN/4
XOUT
Figure 10-2 R Oscillator Connections To use the RC oscillation, the CLK option of the configuration bits (20FFH) should be set to "EXRC or EXRCXO". The oscillator frequency, divided by 4, is output from the Xout pin, and can be used for test purpose or to synchronize other logic. In addition to external crystal/resonator and external RC/R oscillation, the MC80F0704/0708/0804/0808 provides the internal 4MHz or 2MHz oscillation. The internal 4MHz/2MHz oscillation needs no external parts. To use the internal 4MHz/2MHz oscillation, the CLK option of the configuration bits should be set to "IN4MCLK", "IN2MCLK", "IN4MCLKXO" or "IN2MCLKXO". For detail description on the configuration bits, refer to "22.. Device Configuration Area" on page 100
External Clock Source
Xin Vss
Figure 10-4 External Clock Connections In addition, the MC80F0704/0708/0804/0808 has an ability for the external RC oscillated operation. It offers additional cost savings for timing insensitive applications. The RC oscillator frequency is a function of the supply voltage, the external resistor (REXT) and capacitor (CEXT) values, and the operating temperature.
August 18, 2009 Ver 1.02
43
www.DataSheet.in
MC80F0704/0708/0804/0808
11. BASIC INTERVAL TIMER
The MC80F0704/0708/0804/0808 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1 . In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2. If the RCWDT bit is set to "1", the clock source of the BITR is changed to the internal RC oscillation. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0F2H is read as a BITR, and written to CKCTLR. Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction.
Internal RC OSC
RCWDT /8 /16 /32 /64 /128 /256 /512 /1024
1 0
source clock
8-bit up-counter overflow BITR BITIF
Basic Interval Timer Interrupt
XIN PIN
Prescaler
MUX
[0F2H] clear
To Watchdog timer (WDTCK)
Select Input clock 3 BCK[2:0] [0F2H] Basic Interval Timer clock control register Internal bus line CKCTLR Read RCWDT BTCL
Figure 11-1 Block Diagram of Basic Interval Timer
44
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
CKCTLR [2:0] 000 001 010 011 100 101 110 111
Source clock fXIN/8 fXIN/16 fXIN/32 fXIN/64 fXIN/128 fXIN/256 fXIN/512 fXIN/1024
Interrupt (overflow) Period (ms) @ fXIN = 8MHz 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768
Table 11-1 Basic Interval Timer Interrupt Period
7
CKCTLR
ADRST
6 -
5
4
3
2
1
0
RCWDT WDTONBTCL BTCL
BTS2 BTS1 BTS0
ADDRESS: 0F2H INITIAL VALUE: 0-01 0111B
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
Basic Interval Timer source clock select 000: fXIN / 8 001: fXIN / 16 010: fXIN / 32 011: fXIN / 64 100: fXIN / 128 101: fXIN / 256 110: fXIN / 512 111: fXIN / 1024 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after one machine cycle, and starts counting. Watchdog timer Enable bit 0: Operate as 7-bit Timer 1: Enable Watchdog Timer operation See the section "Watchdog Timer". RC Watchdog Selection bit 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer Address Trap Reset Selection 0: Enable Address Fail Reset 1: Disable Address Fail Reset
7
6
5
4
BITR
3 BTCL
2
1
0
ADDRESS: 0F2H INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. : LDM SET1 EI : CKCTLR,#1BH BITE Example 2: Interrupt request flag is generated every 8.192ms at 8MHz. : LDM SET1 EI : CKCTLR,#1CH BITE
August 18, 2009 Ver 1.02
45
www.DataSheet.in
MC80F0704/0708/0804/0808
12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the XIN pin. It means that the watchdog timer will run, even if the clock on the XIN pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM LDM LDM STOP NOP NOP : CKCTLR,#3FH; enable the RC-OSC WDT WDTR,#0FFH ; set the WDT period SSCR, #5AH ;ready for STOP mode ; enter the STOP mode ; RC-OSC WDT running
The RC-WDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 33~100uS). The following equation shows the RCWDT oscillated watchdog timer time-out. TRCWDT=CLKRCWDTx28xWDTR + (CLKRCWDTx28)/2 where, CLKRCWDT = 33~100uS In addition, this watchdog timer can be used as a simple 7-bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = (WDTR+1) x Interval of BIT
clear BASIC INTERVAL TIMER OVERFLOW Watchdog Counter (7-bit) clear
Count source
"0" comparator WDTCL 7-bit compare data 7 WDTR [0F4H] Internal bus line Watchdog Timer Register "1" enable
to reset CPU
WDTON in CKCTLR [0F2H] WDTIF
Watchdog Timer interrupt
Figure 12-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
Figure 12-2 shows the watchdog timer control register. The
watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the detection
46
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to
W 7 W 6 W 5 W 4 W 3 W 2
low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. The WDTON bit is in register CLKCTLR. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting).
W 1 W 0
WDTR
WDTCL
ADDRESS: 0F4H INITIAL VALUE: 0111 1111B
7-bit compare data Clear count flag 0: Free-run count 1: When the WDTCL is set to "1", binary counter is cleared to "0". And the WDTCL becomes "0" automatically after one machine cycle. Counter count up again.
Figure 12-2 WDTR: Watchdog Timer Control Register Example: Sets the watchdog timer detection time to 1 sec. at LDM LDM 4.194304MHz
CKCTLR,#3FH ;Select 1/1024 clock source, WDTON 1, Clear Counter WDTR,#08FH
LDM WDTR,#08FH ;Clear counter : : Within WDT : detection time : LDM WDTR,#08FH ;Clear counter : : Within WDT : detection time : LDM WDTR,#08FH ;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to "1". WDTON is initialized to "0" during reset and it should be set to "1" to operate after reset is released. Example: Enables watchdog timer for Reset : LDM : : CKCTLR,#xxx1_xxxxB;WDTON 1
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit timer by clearing bit4 of CKCTLR to "0". The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. TWDT = (WDTR+1) x Interval of BIT The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Example: 7-bit timer interrupt set up. LDM LDM : CKCTLR,#xxx0_xxxxB;WDTON 0 WDTR,#8FH ;WDTCL 1
The watchdog timer is disabled by clearing bit 4 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released.
August 18, 2009 Ver 1.02
47
www.DataSheet.in
MC80F0704/0708/0804/0808
Source clock BIT overflow Binary-counter
1 2 3 0 Counter Clear 1 2 3 0 Counter Clear 3 Match Detect
WDTR WDTIF interrupt
n
WDTR "1000_0011B" WDT reset reset
Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode.
48
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
13. TIMER/EVENT COUNTER
The MC80F0704/0708/0804/0808 has Four Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Counter with combine them. Also Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency. In the "counter" function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0 or EC1. In addition the "capture" function, the register is increased in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into Timer data register correspondingly. When external clock edge input, the count register is captured into capture data register CDRx. Timer 0 and Timer 1 is shared with "PWM" function and "Compare output" function. It has six operating modes: "8-bit timer/ counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", and "10-bit PWM" which are selected by bit in Timer mode register TM0 and TM1 as shown in Table 13-1, Figure 13-1 . Timer 2 and Timer 3 is shared with "PWM" function and "Compare output" function. It has six operating modes: "8-bit timer/ counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", and "10-bit PWM" which are selected by bit in Timer mode register TM2 and TM3 as shown in Table 13-2, Figure 13-2 .
16BIT 0 0 0 0 1 1 1
CAP0 0 0 1 X 0 0 1
CAP1 0 1 0 0 0 0 1
PWM1E 0 0 0 1 0 0 0
T0CK [2:0] XXX 111 XXX XXX XXX 111 XXX
T1CK [1:0] XX XX XX XX 11 11 11
PWM1O 0 0 1 1 0 0 0
TIMER 0 8-bit Timer 8-bit Event counter 8-bit Capture (internal clock) 8-bit Timer/Counter 16-bit Timer 16-bit Event counter 16-bit Capture (internal clock)
TIMER 1 8-bit Timer 8-bit Capture 8-bit Compare Output 10-bit PWM
Table 13-1 Operation Modes of Timer 0, 1 1. X means the value of "0" or "1" corresponds to user operation.
16BIT 0 0 0 0 1 1 1
CAP2 0 0 1 X 0 0 1
CAP3 0 1 0 0 0 0 1
PWM3E 0 0 0 1 0 0 0
T2CK [2:0] XXX 111 XXX XXX XXX 111 XXX
T3CK [1:0] XX XX XX XX 11 11 11
PWM3O 0 0 1 1 0 0 0
TIMER 2 8-bit Timer 8-bit Event counter 8-bit Capture (internal clock) 8-bit Timer/Counter 16-bit Timer 16-bit Event counter 16-bit Capture (internal clock)
TIMER 3 8-bit Timer 8-bit Capture 8-bit Compare Output 10-bit PWM
Table 13-2 Operating Modes of Timer 2, 3
August 18, 2009 Ver 1.02
49
www.DataSheet.in
MC80F0704/0708/0804/0808
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T0ST
TM0
-
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN BTCL
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
Bit Name CAP0 T0CK2 T0CK1 T0CK0
Bit Position TM0.5 TM0.4 TM0.3 TM0.2
Description 0: Timer/Counter mode 1: Capture mode selection flag 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 32 100: 8-bit Timer, Clock source is fXIN / 128 101: 8-bit Timer, Clock source is fXIN / 512 110: 8-bit Timer, Clock source is fXIN / 2048 111: EC0 (External clock) 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T0CN T0ST
TM0.1 TM0.0
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
TM1
POL
16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST BTCL
ADDRESS: 0D2H INITIAL VALUE: 00H
Bit Name POL 16BIT PWM1E CAP1 T1CK1 T1CK0
Bit Position TM1.7 TM1.6 TM1.5 TM1.4 TM1.3 TM1.2
Description 0: PWM Duty Active Low 1: PWM Duty Active High 0: 8-bit Mode 1: 16-bit Mode 0: Disable PWM 1: Enable PWM 0: Timer/Counter mode 1: Capture mode selection flag 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN / 2 10: 8-bit Timer, Clock source is fXIN / 8 11: 8-bit Timer, Clock source is Using the Timer 0 Clock 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T1CN T1ST
TM1.1 TM1.0
TDR0 TDR1
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
ADDRESS: 0D1H INITIAL VALUE: 0FFH ADDRESS: 0D3H INITIAL VALUE: 0FFH
Read: Count value read Write: Compare data write
Figure 13-1 TM0, TM1 Registers
50
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T2ST
TM2
-
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN BTCL
ADDRESS: 0D6H INITIAL VALUE: --00 0000B
Bit Name CAP2 T2CK2 T2CK1 T2CK0
Bit Position TM2.5 TM2.4 TM2.3 TM2.2
Description 0: Timer/Counter mode 1: Capture mode selection flag 000: 8-bit Timer, Clock source is fXIN / 2 001: 8-bit Timer, Clock source is fXIN / 4 010: 8-bit Timer, Clock source is fXIN / 8 011: 8-bit Timer, Clock source is fXIN / 16 100: 8-bit Timer, Clock source is fXIN / 64 101: 8-bit Timer, Clock source is fXIN / 256 110: 8-bit Timer, Clock source is fXIN / 1024 111: EC1 (External clock) 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T2CN T2ST
TM2.1 TM2.0
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
TM3
POL
16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL
ADDRESS: 0D8H INITIAL VALUE: 00H
Bit Name POL 16BIT PWM3E CAP3 T3CK1 T3CK0
Bit Position TM3.7 TM3.6 TM3.5 TM3.4 TM3.3 TM3.2
Description 0: PWM Duty Active Low 1: PWM Duty Active High 0: 8-bit Mode 1: 16-bit Mode 0: Disable PWM 1: Enable PWM 0: Timer/Counter mode 1: Capture mode selection flag 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN / 4 10: 8-bit Timer, Clock source is fXIN / 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock 0: Timer count pause 1: Timer count start 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again.
T3CN T3ST
TM3.1 TM3.0
TDR2 TDR3
R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
ADDRESS: 0D7H INITIAL VALUE: 0FFH ADDRESS: 0D9H INITIAL VALUE: 0FFH
Read: Count value read Write: Compare data write
Figure 13-2 TM2, TM3 Registers
August 18, 2009 Ver 1.02
51
www.DataSheet.in
MC80F0704/0708/0804/0808
13.1 8-bit Timer / Counter Mode
The MC80F0704/0708/0804/0808 has four 8-bit Timer/ Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in Figure 13-3 and Timer 2, Timer 3 are shown in Figure 13-4 . The "timer" or "counter" function is selected by control registers TM0, TM1, TM2, TM3 as shown in Figure 13-1 . To use as an 8bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of TMx should be cleared to "0" and 16BIT and PWM1E or PWM3E of TM1 or TM3 should be cleared to "0" (Figure 13-3 ). These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external clock (selected by control bits TxCK0, TxCK1, TxCK2 of register TMx).
7
6 -
5 0
4 X
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 0 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H
TM1
POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST BTCL X 0 X X X X
X means don't care
T0CK[2:0] EDGE DETECTOR
EC0 PIN
/2 /4 Prescaler /8 / 32 / 128 / 512 / 2048
111 T0ST 000 001 010 011 100 101 110 MUX T0CN Comparator 0: Stop 1: Clear and start T0 (8-bit) clear T0IF TIMER 0 INTERRUPT
XIN PIN
TIMER 0
TDR0 (8-bit)
F/F
R05 / T0O
T1CK[1:0] T1ST /1 /2 /8 11 00 01 10 MUX T1CN Comparator T1IF 0: Stop 1: Clear and start T1 (8-bit) clear TIMER 1 INTERRUPT
TIMER 1
TDR1 (8-bit)
Figure 13-3 8-bit Timer/Counter 0, 1
52
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
7
6 -
5 0
4 X
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL X X X X
ADDRESS: 0D6H INITIAL VALUE: --000000B
X means don't care 7 6 5 0 4 0 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 X X X X
X means don't care
T2CK[2:0] EDGE DETECTOR
EC1 PIN
/2 /4 Prescaler /8 / 16 / 64 / 256 / 1024
111 T2ST 000 001 010 011 100 101 110 MUX T2CN Comparator 0: Stop 1: Clear and start T2 (8-bit) clear T2IF TIMER 2 INTERRUPT
XIN PIN
TIMER 2
TDR2 (8-bit)
F/F
R06 / T2O
T3CK[1:0] T3ST /1 /4 / 16 11 00 01 10 MUX T3CN Comparator T3IF 0: Stop 1: Clear and start T3 (8-bit) clear TIMER 3 INTERRUPT
TIMER 3
TDR3 (8-bit)
Figure 13-4 8-bit Timer/Counter 2, 3
August 18, 2009 Ver 1.02
53
www.DataSheet.in
MC80F0704/0708/0804/0808
Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 1ms 8-bit timer mode at 4MHz Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 8-bit event counter mode Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0001_1111B TM1,#0000_1011B TM2,#0001_1111B TM3,#0000_1011B T0E T1E T2E T3E TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0000_1111B TM1,#0000_1011B TM2,#0000_1111B TM3,#0000_1011B T0E T1E T2E T3E
These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of register TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of register TM3. In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). In counter function, the counter is increased every 0-to-1 (rising edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the Port Selection Register (PSR0.4) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Likewise, In order to use Timer2 as counter function, the bit EC1 of the Port Selection Register (PSR0.5) is set to "1". The Timer 2 can be used as a counter by pin EC1 input, but Timer 3 can not.
8-bit Timer Mode
In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you want.
Start count
Source clock
~ ~ ~ ~ n-2 n-1 n 1 2 3 4
Up-counter TDR1 T1IF interrupt
0 n
1
2
3 ~ ~ ~ ~ ~ ~
0
Match Detect
Counter Clear
Figure 13-5 Timer Mode Timing Chart
54
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Example: Make 1ms interrupt using by Timer0 at 4MHz LDM LDM SET1 EI
When
TM0,#0FH TDR0,#124 T0E
; ; ; ;
divide by 32 8us x (124+1)= 1ms Enable Timer 0 Interrupt Enable Master Interrupt
TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32) TDR0 = 124D = 7CH fXIN = 4 MHz 1 INTERRUPT PERIOD = x 32 x (124+1) = 1 ms 4 x 106 Hz TDR0 7C
nt ou
MATCH (TDR0 = T0) 7C 7B 7A
~~
Count Pulse Period
~~
up -c
8 s
~~
6 5 4 3 2 1
0
0 Interrupt period = 8 s x (124+1)
TIME
Timer 0 (T0IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 13-6 Timer Count Example
8-bit Event Counter Mode
In this mode, counting up is started by an external trigger. This trigger means rising edge of the EC0 or EC1 pin input. Source clock is used as an internal clock selected with timer mode register TM0 or TM2. The contents of timer data register TDRn (n = 0,1,2,3) are compared with the contents of the up-counter Tn. If a match is found, an timer interrupt request flag TnIF is generated, and the counter is cleared to "0". The counter is restart and count up continuously by every rising edge of the EC0 or EC1 pin input. The maximum frequency applied to the EC0 or EC1 pin is fXIN/ 2 [Hz].
In order to use event counter function, the bit 4, 5 of the Port Selection Register PSR0(address 0F8H) is required to be set to "1". After reset, the value of timer data register TDRn is initialized to "0", The interval period of Timer is calculated as below equation. 1Period (sec) = ---------- x 2 x Divide Ratio x (TDRn+1)
f XIN
Start count EC0 pin input ~ ~ ~ ~ 1 n
Up-counter TDR0 T1IF interrupt
0
2
n-1
n
0
1
2
Figure 13-7 Event Counter Mode Timing Chart
~ ~ ~ ~ ~ ~ ~ ~
August 18, 2009 Ver 1.02
55
www.DataSheet.in
MC80F0704/0708/0804/0808
TDR1 disable enable
clear & start stop
up
-c
ou
nt
~ ~
~ ~
TIME Timer 1 (T1IF) Interrupt Occur interrupt T1ST = 1 T1ST = 0 T1CN = 1 T1CN = 0 Occur interrupt
T1ST Start & Stop T1CN Control count
Figure 13-8 Count Operation of Timer / Event counter
56
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
13.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit timer/ counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively as shown in Figure 13-9 . Likewise, A 16-bit timer/counter register T2, T3 are incremented from 0000H until it matches TDR2, TDR3 and then resets to 0000H. The match output generates Timer 2 interrupt. The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively as shown in Figure 13-10 . Even if the Timer 0 (including Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM3. Reversely, even if the Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently.
7
6 -
5 0
4 X
3
2
1
0
TM0
-
BTCL CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 0 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H
TM1
POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST BTCL X 1 1 1 X X
X means don't care T0CK[2:0] EDGE DETECTOR
EC0 PIN
/2
111 000 001 010 011 100 101 110 MUX TDR1 + TDR0 (16-bit) Higher byte Lower byte COMPARE DATA TIMER 0 + TIMER 1 TIMER 0 (16-bit) T0CN Comparator T0ST 0: Stop 1: Clear and start T1 + T0 (16-bit) clear TIMER 0 INTERRUPT (Not Timer 1 interrupt)
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
T0IF
Figure 13-9 16-bit Timer/Counter for Timer 0, 1
August 18, 2009 Ver 1.02
57
www.DataSheet.in
MC80F0704/0708/0804/0808
7
6 -
5 0
4 X
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL X X X X
ADDRESS: 0D6H INITIAL VALUE: --000000B
X means don't care 7 6 5 0 4 0 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 1 1 1 X X
X means don't care T2CK[2:0] EDGE DETECTOR
EC1 PIN
/2
111 000 001 010 011 100 101 110 MUX TDR3 + TDR2 (16-bit) Higher byte Lower byte COMPARE DATA TIMER 2 + TIMER 3 TIMER 2 (16-bit) T2CN Comparator T2ST 0: Stop 1: Clear and start T3 + T2 (16-bit) clear TIMER 2 INTERRUPT (Not Timer 3 interrupt)
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
T2IF
Figure 13-10 16-bit Timer/Counter for Timer 2, 3
13.3 8-bit Compare Output (16-bit)
The MC80F0704/0708/0804/0808 has Timer Compare Output function. To pulse out, the timer match can goes to port pin (T0O or T2O) as shown in Figure 13-3 or Figure 13-4 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, R05/AN5//T0O or R06/AN6/T2O. In this mode, the bit T0OE or T2OE bit of Port Selection register1 (PSR1.0 or PSR1.1) should be set to "1". This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. Oscillation Frequency f COMP = -----------------------------------------------------------------------------------------2 x Prescaler Value x ( TDR + 1 )
13.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 13-11 . Likewise, the Timer 2 capture mode is set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer mode register TM3 for Timer 3) as shown in Figure 13-12 . The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1, T2, T3) increases and matches TDR0 (TDR1, TDR2, TDR3). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period
58
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
of Timer. For example, in Figure 13-14 , the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1,T2,T3), to be captured into registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af-
ter captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Refer to "17.4 External Interrupt" on page 84. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and TDRn are in same address.In the capture
mode, reading operation is read the CDRn, not TDRn because path is opened to the CDRn.
August 18, 2009 Ver 1.02
59
www.DataSheet.in
MC80F0704/0708/0804/0808
7
6 -
5 1
4 X
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 1 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H
TM1
POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST BTCL X 0 T0CK[2:0] X X X X
X means don't care
Edge Detector
EC0 PIN
/2
111 T0ST 000 001 010 011 100 101 110 MUX IEDS[1:0] CDR0 (8-bit) T0CN clear Capture 0: Stop 1: Clear and start T0 (8-bit)
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
"01"
INT0 PIN
"10" T1CK[1:0] "11" T1ST /1 /2 /8 11 00 01 10 MUX T1CN clear Capture
INT0IF
INT0 INTERRUPT
0: Stop 1: Clear and start T1 (8-bit)
CDR1 (8-bit) IEDS[3:2]
"01"
INT1 PIN
"10" "11"
INT1IF
INT1 INTERRUPT
Figure 13-11 8-bit Capture Mode for Timer 0, 1
60
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
7
6 -
5 1
4 X
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL X X X X
ADDRESS: 0D6H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 1 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 T2CK[2:0] X X X X
X means don't care
Edge Detector
EC1 PIN
/2
111 T2ST 000 001 010 011 100 101 110 MUX IEDS[5:4] CDR2 (8-bit) T2CN clear Capture 0: Stop 1: Clear and start T2 (8-bit)
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
"01"
INT2 PIN
"10" T3CK[1:0] "11" T3ST /1 /4 / 16 11 00 01 10 MUX T3CN clear Capture
INT2IF
INT2 INTERRUPT
0: Stop 1: Clear and start T3 (8-bit)
CDR3 (8-bit) IEDS[7:6]
"01"
INT3 PIN
"10" "11"
INT3IF
INT3 INTERRUPT
Figure 13-12 8-bit Capture Mode for Timer 2, 3
August 18, 2009 Ver 1.02
61
www.DataSheet.in
MC80F0704/0708/0804/0808
T0
9 8 7 6 5 4 3 2 1 0
t
n n-1
This value is loaded to CDR0
~ ~
~ ~
up
-c o
un
~ ~
TIME
Ext. INT0 Pin
Interrupt Request ( INT0IF ) Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request ( INT0IF )
20nS Capture ( Timer Stop )
5nS
Delay
Clear & Start
Figure 13-13 Input Capture Operation of Timer 0 Capture mode
Ext. INT0 Pin
Interrupt Request ( INT0IF ) Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H Interrupt Request ( T0IF ) FFH T0 13H 00H 00H FFH
Figure 13-14 Excess Timer Overflow in Capture Mode
62
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
13.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and 16BIT of TM1 should be set to "1" respectively as shown in Figure 13-15 . The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" respectively as shown in Figure 13-16 .
7
6 -
5 1
4 X
3
2
1
0
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL X X X X
ADDRESS: 0D0H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 1 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H
TM1
POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST BTCL X 1 T0CK[2:0] 1 1 X X
X means don't care
Edge Detector
EC0 PIN
/2
111 T0ST 000 001 010 011 100 101 110 MUX IEDS[1:0] T0CN Capture CDR1 + CDR0 (16-bit) Higher byte Lower byte CAPTURE DATA "01" clear 0: Stop 1: Clear and start TDR1 + TDR0 (16-bit)
XIN PIN
Prescaler
/4 /8 / 32 / 128 / 512 / 2048
INT0 PIN
"10" "11"
INT0IF
INT0 INTERRUPT
Figure 13-15 16-bit Capture Mode of Timer 0, 1
August 18, 2009 Ver 1.02
63
www.DataSheet.in
MC80F0704/0708/0804/0808
7
6 -
5 1
4 X
3
2
1
0
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL X X X X
ADDRESS: 0D6H INITIAL VALUE: --00 0000B
X means don't care 7 6 5 0 4 1 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 1 T2CK[2:0] 1 1 X X
X means don't care
Edge Detector
EC1 PIN
/2
111 T2ST 000 001 010 011 100 101 110 MUX IEDS[5:4] T2CN Capture CDR3 + CDR2 (16-bit) Higher byte Lower byte CAPTURE DATA "01" clear 0: Stop 1: Clear and start TDR3 + TDR2 (16-bit)
XIN PIN
Prescaler
/4 /8 / 16 / 64 / 256 / 1024
INT2 PIN
"10" "11"
INT2IF
INT2 INTERRUPT
Figure 13-16 16-bit Capture Mode of Timer 2, 3 Example 1: Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM LDM LDM LDM SET1 EI : : Example 2: Timer0 = 16-bit event counter mode LDM LDM LDM LDM LDM SET1 EI : : PSR0,#0001_0000B;EC0 Set TM0,#0001_1111B;Counter Mode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; T0E TM0,#0000_1111B;8uS TM1,#0100_1100B;16bit Mode TDR0,#<62499 ;8uS X 62500 TDR1,#>62499 ;=0.5s T0E Example 3: Timer0 = 16-bit capture mode LDM LDM LDM LDM LDM LDM SET1 EI : : PSR0,#0000_0001B;INT0 set TM0,#0010_1111B;Capture Mode TM1,#0100_1100B;16bit Mode TDR0,#<0FFH ; TDR1,#>0FFH ; IEDS,#01H;Falling Edge T0E
64
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
13.6 PWM Mode
The MC80F0704/0708/0804/0808 has high speed PWM (Pulse Width Modulation) functions which shared with Timer1 or Timer3. In PWM mode, R10 / PWM1O or R11 / PWM3O pin output up to a 10-bit resolution PWM output. These pins should be configured as a PWM output by setting "1" bit PWM1OE and PWM3OE in PSR0 register. The period of the PWM1 output is determined by the T1PPR (T1 PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM High Register) and the duty of the PWM output is determined by the T1PDR (T1 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T1 PWM High Register). The period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM High Register) and the duty of the PWM output is determined by the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). The user writes the lower 8-bit period value to the T1(3)PPR and the higher 2-bit period value to the T1(3)PWHR[3:2]. And writes duty value to the T1(3)PDR and the T1(3)PWHR[1:0] same way. The T1(3)PDR is configured as a double buffering for glitchless PWM output. In Figure 13-18 , the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM1(3) Period = [PWM1(3)HR[3:2]T(2)3PPR] X Source Clock PWM1(3) Duty = [PWM1(3)HR[1:0]T3PDR] X Source Clock resolution. Frequency Resolution 10-bit 9-bit 8-bit 7-bit T1CK[1:0] = 00(250nS) 3.9kHz 7.8kHz 15.6kHz 31.2kHz T1CK[1:0] = 01(500nS) 0.98kHz 1.95kHz 3.90kHz 7.81kHz T1CK[1:0] = 10(2uS) 0.49kHz 0.97kHz 1.95kHz 3.90kHz
Table 13-3 PWM Frequency vs. Resolution at 4MHz The bit POL of TM1 or TM3 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 13-20 . As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Note: If changing the Timer1 to PWM function, it should be stop
the timer clock firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values. Ex) Sample Program @4MHz 2uS
The relation of frequency and resolution is in inverse proportion. Table 13-3 shows the relation of PWM frequency vs. resolution. If it needed more higher frequency of PWM, it should be reduced
LDM LDM LDM LDM LDM
TM1,#1010_1000b ; Set Clock & PWM3E T1PPR,#199 ; Period :400uS=2uSX(199+1) T1PDR,#99 ; Duty:200uS=2uSX(99+1) PWM1HR,00H TM1,#1010_1011b ; Start timer1
August 18, 2009 Ver 1.02
65
www.DataSheet.in
MC80F0704/0708/0804/0808
R/W 7
R/W 6
R/W 5 1
R/W 4 0
R/W 3
R/W 2
R/W 1
R/W 0
TM1
POL 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 X X X X
ADDRESS: 0D2H INITIAL VALUE: 00H X:The value "0" or "1" corresponding your operation.
7
6 -
5
-
4 -
W 3
W 2
W 1
W 0
T1PWHR
-
T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 BTCL
ADDRESS: 0D5H INITIAL VALUE: ---- 0000B Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
-
X
X
X
X
Period High
Duty High
W 7
W 6
W 5
W 4
W 3 BTCL
W 2
W 1
W 0
T1PPR
ADDRESS: 0D3H INITIAL VALUE: 0FFH
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3 BTCL
R/W 2
R/W 1
R/W 0
T1PDR
ADDRESS: 0D4H INITIAL VALUE: 00H
T1PWHR[1:0] T0 clock source [T0CK] T1CK[1:0] PWM1OE [PSR0.6] SQ
Clear
T1ST 0 : Stop 1 : Clear and Start
T1PPR(8-bit)
11 Prescaler /1 /2 /8 00 01 10 MUX T1CN
Comparator
R 2-bit
T1(8-bit)
XIN PIN
R10 / PWM1O PIN
POL
Comparator
Slave
T1PDR(8-bit)
T1PWHR[1:0]
Master
T1PDR(8-bit)
Figure 13-17 PWM1 Mode
66
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
R/W 7
R/W 6
R/W 5 1
R/W 4 0
R/W 3
R/W 2
R/W 1
R/W 0
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST BTCL X 0 X X X X
ADDRESS: 0D8H INITIAL VALUE: 00H X:The value "0" or "1" corresponding your operation.
7
6 -
5
-
4 -
W 3
W 2
W 1
W 0
T3PWHR
-
T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 BTCL
ADDRESS: 0DBH INITIAL VALUE: ---- 0000B Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
-
X
X
X
X
Period High
Duty High
W 7
W 6
W 5
W 4
W 3 BTCL
W 2
W 1
W 0
T3PPR
ADDRESS: 0D9H INITIAL VALUE: 0FFH
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3 BTCL
R/W 2
R/W 1
R/W 0
T3PDR
ADDRESS: 0DAH INITIAL VALUE: 00H
T3PWHR[1:0] T2 clock source [T2CK] T3CK[1:0] PWM3O [PSR0.7] SQ
Clear
T3ST 0 : Stop 1 : Clear and Start
T3PPR(8-bit)
11 Prescaler /1 /4 / 16 00 01 10 MUX T3CN
Comparator
R 2-bit
T3(8-bit)
XIN PIN
R11 / PWM3O PIN
POL
Comparator
Slave
T3PDR(8-bit)
T3PWHR[1:0]
Master
T3PDR(8-bit)
Figure 13-18 PWM3 Mode
August 18, 2009 Ver 1.02
67
www.DataSheet.in
MC80F0704/0708/0804/0808
~ ~
~ ~
Source clock T1 PWM1E T1ST T1CN PWM1O [POL=1] PWM1O [POL=0]
00 01 02 03 04
~~ ~~
Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T1CK[1:0] = 00 ( XIN ) T1PWHR = 0CH T1PPR = FFH T1PDR = 7FH
Duty T1PWHR1 0 T1PWHR0 0 T1PDR (8-bit) 7FH
~ ~
Period
T1PWHR3 1
T1PWHR2 1
T1PPR (8-bit) FFH
Figure 13-19 Example of PWM1 at 4MHz
T1CK[1:0] = 10 ( 1us ) PWM1HR = 00H T1PPR = 0DH T1PDR = 04H Source clock T1 PWM1O POL=1 Duty Cycle [ (04h+1) x 2uS = 10uS ] Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ] Duty Cycle [ (04h+1) x 2uS = 10uS ] Duty Cycle [ (04h+1) x 2uS = 10uS ]
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04
Write T1PPR to 09H
Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]
Figure 13-20 Example of Changing the PWM1 Period in Absolute Duty Cycle (@4MHz)
68
~ ~
~~~ ~~~ ~ ~ ~ ~ ~ ~
7E
7F
80
3FF
00
01
02
~ ~
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 10-bit digital value. The A/ D module has sixteen analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is selected to VDD or AVref by setting of the bit AVREFS in PSR1 register. If external analog reference AVref is selected, the analog input channel 0 (AN0) should not be selected to use. Because this pin is used to an analog reference of A/D converter. The A/D module has three registers which are the control register ADCM and A/D result register ADCRH and ADCRL. The ADCRH[7:6] is used as ADC clock source selection bits too. The register ADCM, shown in Figure 14-4 , controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. It is selected for the corresponding channel to be converted by setting ADS[3:0]. The A/D port is set to analog input port by ADEN and ADS[3:0] regardless of port I/O direction register. The port unselected by ADS[3:0] operates as normal port. set to "1". After one cycle, it is cleared by hardware. The register ADCRH and ADCRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCRH and ADCRL, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADCIF is set. See Figure 14-1 for operation flow. The block diagram of the A/D module is shown in Figure 14-3 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes 13 times of conversion source clock. The conversion source clock should selected for the conversion time being more than 25s.
A/D Converter Cautions
(1) Input range of AN0 ~ AN15 The input voltage of A/D input pins should be within the specification range. In particular, if a voltage above VDD (or AVref) or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. (2) Noise countermeasures In order to maintain 10-bit resolution, attention must be paid to noise on pins VDD (or AVref) and analog input pins (AN0 ~ AN15). Since the effect increases in proportion to the output impedance of the analog input source, it is recommended in some cases that a capacitor be connected externally as shown in Figure 14-2 in order to reduce noise. The capacitance is user-selectable and appropriately determined according to the target system.
Enable A/D Converter
A/D Input Channel Select
Conversion Source Clock Select
A/D Start (ADST = 1)
Analog Input 0~1000pF User Selectable
AN0~AN15
NOP
ADSF = 1 NO YES Read ADCR
Figure 14-2 Analog Input Pin Connecting Capacitor (3) I/O operation The analog input pins AN0 ~ AN15 also have function as input/ output port pins. When A/D conversion is performed with any pin, be sure not to execute a PORT input instruction with the selected pin while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value
Figure 14-1 A/D Converter Operation Flow
How to Use A/D Converter
The processing of conversion is start when the start bit ADST is
August 18, 2009 Ver 1.02
69
www.DataSheet.in
MC80F0704/0708/0804/0808
may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVDD pin input impedance A series resistor string of approximately 5K is connected between the AVREF pin and the VSS pin. Therefore, if the output impedance of the analog power source is high, this will result in parallel connection to the series resistor string between the AVREF pin and the VSS pin, and there will be a large analog sup-
ply voltage error Note: If the AVREF voltage is less than VDD voltage and anlalog input pins(ANX), shared with various alternate function, are used bidirectional I/O port, the leakage current may flow VDD pin to AVREF pin in output high mode or anlalog input pins(ANX) to AVREF pin in input high mode.
AVREFS (PSR1.3) ADEN
VDD
0 Resistor Ladder Circuit 1
AN0 / AVREF AN1
Successive MUX Sample & Hold Approximation Circuit ADCIF
ADC INTERRUPT
AN14 AN15
ADC8 0 1
10-bit Mode ADS[3:0] (ADCM[5:2]) 98 ADCRADCR 10-bit (10-bit) 00 ADCRH 10 ADC Result Register ADCRL (8-bit) ADCRH 10 98
8-bit Mode
32
10-bit ADCR
ADCRL (8-bit)
ADC Result Register
Figure 14-3 A/D Block Diagram
70
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
ADCM
R/W R/W R/W R 3 2 1 0 ADS1 ADEN ADCK ADS3 ADS2 BTCL ADS0 ADST ADSF R/W 7 R/W 6
R/W 5
R/W 4
ADDRESS: 0EFH INITIAL VALUE: 0000 0001B A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0" by hardware.
Analog input channel select 0000: Channel 0 (AN0) 0110: Channel 6 (AN6) 0001: Channel 1 (AN1) 0111: Channel 7 (AN7) 0010: Channel 2 (AN2) 1000: Channel 8 (AN8) 0011: Channel 3 (AN3) 1001: Channel 9 (AN9) 0100: Channel 4 (AN4) 1010: Channel 10 (AN10) 0101: Channel 5 (AN5) 1011: Channel 11 (AN11)
1100: Channel 12 (AN12) 1101: Channel 13 (AN13) 1110: Channel 14 (AN14) 1111: Channel 15 (AN15)
A/D converter Clock Source Divide Ratio Selection bit 0: Clock Source fPS 1: Clock Source fPS / 2 A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter W 7 W 6 W 5 4 3 BTCL 2 R 1 R 0 ADDRESS: 0F0H INITIAL VALUE: 010- ----B A/D Conversion High Data ADC 8-bit Mode select bit 0: 10-bit Mode 1: 8-bit Mode A/D Conversion Clock (fPS) Source Selection 00: fXIN / 4 01: fXIN / 8 10: fXIN / 16 11: fXIN / 32 ~ 1101: Not available
ADCRH
PSSEL1 PSSEL0 ADC8
R 7
R 6
R 5
R 4
ADCRL
R 3 BTCL
R 2
R 1
R 0
ADDRESS: 0F1H INITIAL VALUE: Undefined A/D Conversion Low Data
ADCK 0 0 0 0 1 1 1 1
PSSEL1 0 0 0 0 1 1 1 1
PSSEL0 0 1 0 1 0 1 0 1
PS Clock Selection PS = fXIN / 4 PS = fXIN / 8 PS = fXIN / 16 PS = fXIN / 32 PS = fXIN / 64 PS = fXIN / 128 PS = fXIN / 256 PS = fXIN / 512 PS : Conversion Clock
Figure 14-4 A/D Converter Control & Result Register
August 18, 2009 Ver 1.02
71
www.DataSheet.in
MC80F0704/0708/0804/0808
15. SERIAL INPUT/OUTPUT (SIO)
The serial Input/Output is used to transmit/receive 8-bit data serially. The Serial Input/Output (SIO) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. This SIO is 8bit clock synchronous type and consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 15-1 . The SO pin is designed to input and output. So the Serial I/O(SIO) can be operated with minimum two pin. Pin R00/SCK, R01/SI, and R02/SO pins are controlled by the Serial Mode Register. The contents of the Serial I/O data register can be written into or read out by software. The data in the Serial Data Register can be shifted synchronously with the transfer clock signal.
SIOST SCK[1:0] /4 / 16 POL 00 01 10 11 "0" Clock "1" Start
SIOSF clear
XIN PIN
Timer0 Overflow
Prescaler
Complete
overflow
SIO CONTROL CIRCUIT
Clock
Octal Counter (3-bit)
SIOIF Serial communication Interrupt
SCK PIN
"11" not "11" SCK[1:0]
MUX
SM0 SOUT
IOSW
SO PIN
IOSW 1 Input shift register 0 Shift SIOR
SI PIN
Internal Bus
Figure 15-1 SIO Block Diagram
72
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Serial I/O Mode Register (SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected.
Serial I/O Data Register (SIOR) is an 8-bit shift register. First LSB is send or is received first.
R/W 7
R/W 6
R/W 5
SIOM
POL IOSW SM1
R/W R/W R/W R 3 2 1 0 SM0 BTCL SCK0 SIOST SIOSF SCK1
R/W 4
ADDRESS: 0E2H INITIAL VALUE: 0000 0001B Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to "0" by hardware. Serial transmission Clock selection 00: fXIN / 4 01: fXIN / 16 10: TMR0OV(Timer0 Overflow) 11: External Clock Serial transmission Operation Mode 00: Normal Port (R00,R01,R02) 01: Sending Mode (SCK,R01,SO) 10: Receiving Mode (SCK,SI,R02) 11: Sending & Receiving Mode (SCK,SI,SO) Serial Input Pin Selection bit 0: SI Pin Selection 1: SO Pin Selection
Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BTCL
SIOR
ADDRESS: 0E3H INITIAL VALUE: Undefined
Sending Data at Sending Mode Receiving Data at Receiving Mode
Figure 15-2 SIO Control Register
15.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM) to "1". After one cycle of SCK, SIOST and SIOSF (bit 0 of SIOM) is cleared automatically to "0". At the default state of POL bit clear, the serial output data from 8-bit shift register is output at falling edge of SCLK, and input data is latched at rising edge of SCLK pin (Refer to Figure 15-3 ). When transmission clock is counted 8 times, serial I/O counter is cleared as `0". Transmission clock is halted in "H" state and serial I/O interrupt (SIOIF) occurred. SIOSF is set to "1" automatically.
August 18, 2009 Ver 1.02
73
www.DataSheet.in
MC80F0704/0708/0804/0808
SIOST SCK [R00] (POL=0)
SO [R02] SI [R01] (IOSW=0) IOSWIN [R02] (IOSW=1) SIOIF (SIO Int. Req) SIOSF (SIO Status)
D0 D0 D0
D1 D1 D1
D2 D2 D2
D3 D3 D3
D4 D4 D4
D5 D5 D5
D6 D6 D6
D7 D7 D7
Figure 15-3 Serial I/O Timing Diagram at POL=0
SIOST SCK [R00] (POL=1)
SO [R02] SI [R01] (IOSW=0) IOSWIN [R02] (IOSW=1) SIOIF (SIO Int. Req) SIOSF (SIO Status)
D0 D0 D0
D1 D1 D1
D2 D2 D2
D3 D3 D3
D4 D4 D4
D5 D5 D5
D6 D6 D6
D7 D7 D7
Figure 15-4 Serial I/O Timing Diagram at POL=1
74
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
15.2 The usage of Serial I/O
1. Select transmission/receiving mode. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to "1" to start serial transmission. 4. The SIO interrupt is generated at the completion of SIO and SIOIF is set to "1". 5. In case of receiving mode, the received data is acquired by reading the SIOR. 6. When using polling method, the completion of 1 byte serial communication can be checked by reading SIOST and SIOSF. As shown in example code, wait until SIOST is changed to "0" and then wait the SIOSF is changed to "1" for completion check.
LDM SIOR,#0AAh ;set tx data LDM SIOM,#0011_1100b;set SIO mode NOP LDM SIOM,#0011_1110b;SIO Start NOP SIO_WAIT: NOP BBS SIOST,SIO_WAIT ;wait first edge BBC SIOSF,SIO_WAIT ;wait complete
Note: When external clock is used, the frequency should be less
than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is performed simultaneously, error may be occur.
August 18, 2009 Ver 1.02
75
www.DataSheet.in
MC80F0704/0708/0804/0808
16. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter, buzzer register BUZR, and clock source selector. It generates squarewave which has very wide range frequency (488Hz ~ 250kHz at fXIN= 4MHz) by user software. A 50% duty pulse can be output to R12 / BUZO pin to use for piezo-electric buzzer drive. Pin R12 is assigned for output port of Buzzer driver by setting the bit 2 of PSR1(address 0F9H) to "1". For PSR1 register, refer to Figure 16-2 . Example: 5kHz output at 4MHz. LDM LDM
X means don't care
driving. Equation of frequency calculation is shown below.
f XIN f BUZ = -------------------------------------------------------------------------------2 x DivideRatio x ( BUR + 1 )
fBUZ: Buzzer frequency fXIN: Oscillator frequency Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUZR. Buzzer period value.
BUZR,#0011_0001B PSR1,#XXXX_X1XXB
The frequency of output signal is controlled by the buzzer control register BUZR. The bit 0 to bit 5 of BUZR determine output frequency for buzzer driving.
The bit 0 to 5 of BUZR determines output frequency for buzzer
R12 port data /8 Prescaler / 16 / 32 / 64 00 01 10 11 MUX 2 Comparator Compare data 6 BUR [0E0H] Internal bus line BUZO PSR1 [0F9H] Port selection register 1 F/F 6-BIT BINARY COUNTER
XIN PIN
MUX 0 1
R12/BUZO PIN
Figure 16-1 Block Diagram of Buzzer Driver
ADDRESS: 0E0H RESET VALUE: 0FFH W W W W W W W W
ADDRESS: 0F9H RESET VALUE: ---- 0000B
BUZR
BUCK1 BUCK0
PSR1
-
-
-
-
-
BUZO
-
-
BUR[5:0] Buzzer Period Data Source clock select 00: fXIN / 8 01: fXIN / 16 10: fXIN / 32 11: fXIN / 64
R12 / BUZO Selection 0: R12 port (Turn off buzzer) 1: BUZO port (Turn on buzzer)
Figure 16-2 Buzzer Register & PSR1
76
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
The 6-bit counter is cleared and starts the counting by writing signal at BUZR register. It is incremental from 00H until it matches 6-bit BUR value. BUR[7:6] 00 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 01 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 10 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 11 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977
When main-frequency is 4MHz, buzzer frequency is shown as below Table 16-1.
BUR [5:0] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
BUR [5:0] 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
BUR[7:6] 00 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 01 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 10 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 11 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
Table 16-1 buzzer frequency (kHz unit)
August 18, 2009 Ver 1.02
77
www.DataSheet.in
MC80F0704/0708/0804/0808
17. INTERRUPTS
The MC80F0704/0708/0804/0808 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag ("I" flag of PSW). Fifteen interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 17-1 and interrupt priority is shown in Table 17-1. The External Interrupts INT0 ~ INT3 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection IEDS register. The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in register IRQH. When an external interrupt is generated, the generated flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF which is set by a match in their respective timer/ counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion. The Watchdog timer is generated by WDTIF and WTIF which is set by a match in Watchdog timer register.
Internal bus line [0EAH] IENH IRQH [0ECH] INT0 INT1 INT2 INT3 INT0IF INT1IF INT2IF INT3IF Priority Control To CPU I-flag Interrupt Master Enable Flag Interrupt Vector Address Generator Release STOP/SLEEP Interrupt Enable Register (Higher byte) I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
Serial Communication Timer 0 IRQL [0EDH] Timer 1 Timer 2 Timer 3
SIOIF T0IF
T1IF T2IF T3IF
A/D Converter Watchdog Timer
ADCIF WDTIF
BIT
BITIF
[0EBH]
IENL
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 17-1 Block Diagram of Interrupt The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register.
78
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
The SIO interrupt is generated by SIOIF which is set by completion of SIO data reception or transmission. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on Figure 8-3 ), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. The Table 17-1 shows the Interrupt priority. Vector addresses are shown in Figure 8-6 . Interrupt enable registers are shown in Figure 17-2 . These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Reset/Interrupt Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Serial Input/Output Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 ADC Interrupt Watchdog Timer Basic Interval Timer Symbol RESET INT0 INT1 INT2 INT3 SIO Timer 0 Timer 1 Timer 2 Timer 3 ADC WDT BIT Priority 1 2 3 4 5 6 7 8 9 10 11 12 13
Table 17-1 Interrupt Priority
August 18, 2009 Ver 1.02
79
www.DataSheet.in
MC80F0704/0708/0804/0808
R/W
R/W
R/W
R/W
-
-
R/W SIOE
R/W T0E LSB
IENH
INT0E
INT1E INT2E INT3E
ADDRESS: 0EAH INITIAL VALUE: 0000 --00B Timer/Counter 0 interrupt enable flag Serial Communication interrupt enable flag
MSB
External interrupt 3 enable flag External interrupt 2 enable flag External interrupt 1 enable flag External interrupt 0 enable flag
R/W
R/W T2E
R/W T3E
R/W -
R/W
R/W
R/W -
R/W BITE LSB
IENL
T1E MSB
ADCE WDTE
ADDRESS: 0EBH INITIAL VALUE: 000- 00-0B Basic Interval Timer interrupt enable flag Watchdog timer interrupt enable flag A/D Converter interrupt enable flag Timer/Counter 3 interrupt enable flag Timer/Counter 2 interrupt enable flag Timer/Counter 1 interrupt enable flag
Figure 17-2 Interrupt Enable Flag Register
R/W
R/W
R/W
R/W
-
-
R/W
SIOIF
R/W T0IF LSB
IRQH
INT0IF INT1IF INT2IF INT3IF
MSB
ADDRESS: 0ECH INITIAL VALUE: 0000 --00B Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag
External interrupt 3 request flag External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag
R/W
R/W T2IF
R/W T3IF
-
R/W
R/W
-
R/W BITIF LSB
IRQL
T1IF MSB
ADCIF WDTIF
ADDRESS: 0EDH INITIAL VALUE: 000- 00-0B Basic Interval Timer interrupt request flag Watchdog timer interrupt request flag A/D Converter interrupt request flag Timer/Counter 3 interrupt request flag Timer/Counter 2 interrupt request flag Timer/Counter 1 interrupt request flag
80
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Figure 17-3 Interrupt Request Flag Register
17.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 cycles of fXIN (2s at fXIN =4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI].
Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 3. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 4. The instruction stored at the entry address of the interrupt service program is executed.
System clock Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 17-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer Vector Table Address
Entry Address
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
0FFE0H 0FFE1H
012H 0E3H
0E312H 0E313H
0EH 2EH
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.
Clearing Interrupt Request Flag
The Interrupt Request flag may not cleared itself during interrupt acceptance processing. After interrupt acceptance, it should be cleared as shown in interrupt service routine.
August 18, 2009 Ver 1.02
81
www.DataSheet.in
MC80F0704/0708/0804/0808
Note: The MC80F0708 and HMS87C1416B is similar in function, but the interrupt processing method is different. When replacing the HMS87C1416B to MC80F0708, clearing interrupt request flag should be added.
Example: Clearing Interrupt Request Flag T1_INT: CLR1 T1IF ;CLEAR T1 REQUEST
interrupt processing
RETI
;RETURN
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers. Example: Register save using push and pop instructions INTxx: CLR1 PUSH PUSH PUSH INTxxIF A X Y ;CLEAR REQUEST. ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
interrupt processing
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
General-purpose register save/restore using push and pop instructions;
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-5 .
=0
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
TCALL0 ROUTINE
RET
Figure 17-5 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further
82
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
interrupt can be serviced even if certain interrupt is in progress.
Main Program service
TIMER 1 service INT0 service
enable INT0 disable other EI Occur TIMER1 interrupt
Occur INT0
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
enable INT0 enable other
Figure 17-6 Execution of Multi Interrupt Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: CLR1 PUSH PUSH PUSH LDM LDM EI : : T1IF ;Clear Timer1 Request A X Y IENH,#80H ;Enable INT0 only IENL,#0 ;Disable other int. ;Enable Interrupt : : : : LDM LDM POP POP POP RETI
IENH,#0FFH ;Enable all interrupts IENL,#0FFH Y X A
August 18, 2009 Ver 1.02
83
www.DataSheet.in
MC80F0704/0708/0804/0808
17.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0EEH) as shown in Figure 17-7 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.
01
INT0 pin
10 11
INT0IF
INT0 INTERRUPT
01
INT1 pin
10 11
INT1IF
INT1 INTERRUPT
01
INT2 pin
10 11
INT2IF
INT2 INTERRUPT
01
INT3 pin
2 2 IEDS [0EEH] 2 2
10 11
INT3IF
INT3 INTERRUPT
Edge selection Register
Figure 17-7 External Interrupt Block Diagram INT0 ~ INT3 are multiplexed with general I/O ports (R11, R12, R03, R00). To use as an external interrupt pin, the bit of port selection register PSR0 should be set to "1" correspondingly. Example: To use as an INT0 and INT2 : ;**** Set external interrupt port as pull-up state. LDM PU1,#0000_0101B ; ;**** Set port as an external interrupt port LDM PSR0,#0000_0101B ; ;**** Set Falling-edge Detection LDM IEDS,#0001_0001B :
Response Time
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 17-8 shows interrupt response timings.
max. 12 fXIN
8 fXIN
Interrupt Interrupt goes latched active
Interrupt processing
Interrupt routine
Figure 17-8 Interrupt Response Timing Diagram
84
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
MSB W
W
W
W
W
W
W
LSB W ADDRESS: 0EEH INITIAL VALUE: 00H
IEDS
IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L BTCL INT3 INT2 INT1 INT0
Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)
W
W
W
W
W
W
W
W ADDRESS: 0F8H INITIAL VALUE: 00H
PSR0
PWM3O PWM1O EC1E
EC0E BTCL INT2E INT1E INT0E INT3E
MSB 0: R11 1: PWM3O 0: R10 1: PWM1O 0: R07 1: EC1 0: R04 1: EC0
LSB 0: R11 1: INT0 0: R12 1: INT1 0: R03 1: INT2 0: R00 1: INT3
Figure 17-9 IEDS register and Port Selection Register PSR0
August 18, 2009 Ver 1.02
85
www.DataSheet.in
MC80F0704/0708/0804/0808
18. POWER SAVING OPERATION
The MC80F0704/0708/0804/0808 has two power-down modes. In power-down mode, power consumption is reduced considerably. For applications where power consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 18-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to "0Fh"., and STOP mode is entered by STOP instruction after the SSCR register to "5Ah".
18.1 Sleep Mode
In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all peripherals is shown in Table 18-1. SLEEP mode is entered by setting the SSCR register to "0Fh". It is released by Reset or interrupt. To be released by interrupt, interrupt should be enabled before SLEEP mode.
W 7
W 6
W 5
W 4
W 3
W 2
W 1
W 0
SSCR
ADDRESS: 0F5H INITIAL VALUE: 0000 0000B Power Down Control 5AH: STOP mode 0FH: SLEEP mode
NOTE :
To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released. To get into SLEEP mode, SSCR must be set to 0FH.
Figure 18-1 STOP and SLEEP Control Register
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not change the on-chip RAM. Interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer to Figure 18-4 )
When exit from SLEEP mode by reset, enough oscillation stabilizing time is required to normal operation. Figure 18-3 shows the timing diagram. When released from the SLEEP mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before SLEEP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By interrupts, exit from SLEEP mode is shown in Figure 18-2 . By reset, exit from SLEEP mode is shown in Figure 18-3 .
86
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
.
Oscillator (XIN pin) Internal Clock External Interrupt
SLEEP Instruction Executed Normal Operation SLEEP Operation
Figure 18-2 SLEEP Mode Release Timing by External Interrupt
~~ ~~ ~ ~ ~~ ~~ ~ ~
Normal Operation
~~ ~~ ~ ~
Oscillator (XIN pin) CPU Clock RESET Internal RESET
SLEEP Instruction Execution Normal Operation
SLEEP Operation
Figure 18-3 Timing of SLEEP Mode Release by Reset
~ ~ ~ ~ ~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz Normal Operation
~ ~ ~ ~
18.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripheral clock is stopped, but RC-oscillated watchdog timer continue to operate. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. Note: The Stop mode is activated by execution of STOP instruction after setting the SSCR to "5AH". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)
* The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. * The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode.
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize.
August 18, 2009 Ver 1.02
87
www.DataSheet.in
MC80F0704/0708/0804/0808
Note: After STOP instruction, at least two or more NOP instruction should be written. Ex) LDM CKCTLR,#0FH ;more than 20ms LDM SSCR,#5AH STOP NOP ;for stabilization time NOP ;for stabilization time
In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, Peripheral CPU RAM Basic Interval Timer Watchdog Timer Timer/Counter Buzzer, ADC SIO Oscillator I/O Ports Control Registers Internal Circuit Prescaler Address Data Bus Release Source STOP Mode Stop Retain Halted
the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. SLEEP Mode Stop Retain Operates Continuously Stop Operates Continuously Stop Only operate with external clock Oscillation Retain Retain Sleep mode Active Retain Reset, All Interrupts
Stop (Only operates in RC-WDT mode) Halted (Only when the event counter mode is enabled, timer operates normally) Stop Only operate with external clock Stop (XIN=L, XOUT=H) Retain Retain Stop mode Retain Retain Reset, Timer(EC0,1), SIO (ext. clock), Watchdog Timer (RC-WDT mode), External Interrupt
Table 18-1 Peripheral Operation During Power Saving Mode
Release the STOP mode
The source for exit from STOP mode is hardware reset, external interrupt, Timer(EC0,1), WDT, SIO. When releasing from the STOP mode by the SIO(ext.clock), the SIOR has dummy data and the SIOST bit should be cleared after release from the STOP mode. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service
routine. (refer to Figure 18-4 ) When exit from Stop mode by external interrupt, enough oscillation stabilizing time is required to normal operation. Figure 18-5 shows the timing diagram. When released from the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 18-6 .
88
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
STOP INSTRUCTION STOP Mode
Interrupt Request =0
Corresponding Interrupt Enable Bit (IENH, IENL)
IENH or IENL ? =1 STOP Mode Release
Master Interrupt Enable Bit PSW[2]
I-FLAG =1
=0
Interrupt Service Routine
Next INSTRUCTION
Figure 18-4 STOP Releasing Flow by Interrupts .
Oscillator (XIN pin) Internal Clock External Interrupt
~~ ~~
STOP Instruction Executed
~ ~ ~ ~ ~ ~ ~~ ~~
~ ~ ~ ~ ~~ ~~
BIT Counter
n
n+1 n+2
n+3
0 Clear
1
FE
FF
0
1
2
Normal Operation
Stop Operation
Stabilization Time tST > 20ms by software
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms.
Figure 18-5 STOP Mode Release Timing by External Interrupt
August 18, 2009 Ver 1.02
89
www.DataSheet.in
MC80F0704/0708/0804/0808
STOP Mode
~ ~
Oscillator (XI pin) Internal Clock RESET Internal RESET
~ ~
STOP Instruction Execution Time can not be control by software
Figure 18-6 Timing of STOP Mode Release by Reset
18.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) (at RC-watchdog timer mode). Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine(Figure 8-6 ). However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal Reset signal and execute the reset processing(Figure 18-8 ). If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 18-4 ) When exit from Stop mode at Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 18-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 18-8 .
Note: Caution: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM SSCR,#0101_1010B STOP NOP ;for stabilization time NOP ;for stabilization time
The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt or watchdog timer interrupt
~~ ~~ ~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz
~~ ~~ ~ ~
90
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock External Interrupt ( or WDT Interrupt )
~ ~
STOP Instruction Execution
~ ~
Clear Basic Interval Timer
~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2 STOP mode at RC-WDT Mode
00
01
FE
FF
00
00 Normal Operation
~ ~
Normal Operation
Stabilization Time tST > 20mS
Figure 18-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt
RCWDT Mode
~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock RESET RESET by WDT Internal RESET
~ ~
STOP Instruction Execution Time can not be control by software
Figure 18-8 Internal RC-WDT Mode Releasing by Reset
~ ~ ~ ~
Stabilization Time tST = 65.5mS @4MHz
~ ~ ~ ~
August 18, 2009 Ver 1.02
91
www.DataSheet.in
MC80F0704/0708/0804/0808
18.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turnoff output drivers that are sourcing or sinking current, if it is practical.
VDD INPUT PIN internal pull-up OPEN INPUT PIN VDD VDD i=0
VDD
O
i GND VDD
O
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.
Figure 18-9 Application Example of Unused Input Port
OUTPUT PIN ON OPEN ON OFF i GND VDD ON OFF OFF
OUTPUT PIN VDD L ON OFF i GND OFF ON i=0 GND L VDD
O
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port .
In the left case, much current flows from port to GND.
Figure 18-10 Application Example of Unused Output Port
pull-up or other means.
Note: In the STOP operation, the power dissipation associated
with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/ O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by
It should be set properly in order that current flow through port doesn't exist. First consider the port setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or
92
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. The port setting to High or Low is decided by considering its relationship with exter-
nal circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pulldown register, it is set to low.
August 18, 2009 Ver 1.02
93
www.DataSheet.in
MC80F0704/0708/0804/0808
19. RESET
The MC80F0704/0708/0804/0808 supports various kinds of reset as below.
* Power-On Reset (POR) * RESET (external reset circuitry) * Watchdog Timer Timeout Reset * Power-Fail Detection (PFD) Reset * Address Fail Reset
RESET
POR (Power-On Reset)
Noise Canceller
Address Fail reset Overflow PFD (Power-Fail Detection) Clear BIT
S
Q
Internal RESET
R
WDT (WDT Timeout Reset)
Figure 19-1 RESET Block Diagram The on-chip POR circuit holds down the device in RESET until VDD has reached a high enough level for proper operation. It will eliminate external components such as reset IC or external resistor and capacitor for external reset circuit. In addition that the RESET pin can be used to normal input port R35 by setting "POR" On-chip Hardware Program counter RAM page register G-flag Operation mode (PC) (RPR) (G) Initial Value (FFFFH) - (FFFEH) 0 0 Main-frequency clock and "R35EN" bit Configuration Area(20FFH) in the Flash programming. When the device starts normal operation, its operating parameters (voltage, frequency, temperature...etc) must be met. .Table 19-1 shows on-chip hardware initialization by reset action.
On-chip Hardware Peripheral clock Watchdog timer Control registers Power fail detector
Initial Value Off Disable Refer to Table 8-1 on page 29 Disable
Table 19-1 Initializing Internal Status by Reset Action The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 19-3 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 19-2 .
VCC
10k 7036P to the RESET pin
+
10uF
Figure 19-2 Simple Power-on-Reset Circuit
94
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
1
2
3
4
5
6
7
~ ~
Oscillator (XIN pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST =65.5mS at 4MHz
Figure 19-3 Timing Diagram after Reset The Address Fail Reset is the function to reset the system by checking code access of abnormal and unwished address caused by erroneous program code itself or external noise, which could not be returned to normal operation and would become malfunction state. If the CPU tries to fetch the instruction from ineffective code area or RAM area, the address fail reset is occurred. Please refer to Figure 11-2 for setting address fail option.
~ ~
Reset Process Step tST = 1 fXIN /1024 x 256 MAIN PROGRAM
August 18, 2009 Ver 1.02
95
www.DataSheet.in
MC80F0704/0708/0804/0808
20. POWER FAIL PROCESSOR
The MC80F0704/0708/0804/0808 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to "Figure 20-1 Power Fail Voltage Detector Register" on page 96. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated.
PFDR
7 -
6 -
5 -
4 -
3 -
R/W 2
R/W 1
R/W 0
PFDEN PFDM PFDS
ADDRESS: 0F7H INITIAL VALUE: ---- -000B Power Fail Status 0: Normal operate 1: Set to "1" if power fail is detected PFD Operation Mode 0 : MCU will be frozen by power fail detection 1 : MCU will be reset by power fail detection PFD Enable Bit 0: Power fail detection disable 1: Power fail detection enable
* Cautions :
Be sure to set bits 3 through 7 to "0".
Figure 20-1 Power Fail Voltage Detector Register
RESET VECTOR
PFDS =1 NO RAM Clear Initialize RAM Data
YES
PFDS = 0 Skip the initial routine
Initialize All Ports Initialize Registers
Function Execution
Figure 20-2 Example S/W of Reset flow by Power fail
96
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
VDD Internal RESET VDD When PFDM = 1 Internal RESET VDD Internal RESET 65.5mS t < 65.5mS 65.5mS 65.5mS
VPFDMAX VPFDMIN
VPFDMAX VPFDMIN
VPFDMAX VPFDMIN
Figure 20-3 Power Fail Processor Situations (at 4MHz operation)
August 18, 2009 Ver 1.02
97
www.DataSheet.in
MC80F0704/0708/0804/0808
21. COUNTERMEASURE OF NOISE
21.1 Oscillation Noise Protector
The Oscillation Noise Protector (ONP) is used to supply stable internal system clock by excluding the noise which could be entered into oscillator and recovery the oscillation fail. This function could be enabled or disabled by the "ONP" bit of the Device configuration area (20FFH) for the MC80F0704/0708/0804/ 0808, "ONP" option bits MASK option. The ONP function is like below. - Recovery the oscillation wave crushed or loss caused
XIN 1
by high frequency noise. - Change system clock to the internal oscillation clock when the high frequency noise is continuing. - Change system clock to the internal oscillation clock when the XIN/XOUT is shorted or opened, the main oscillation is stopped except by stop instruction and the low frequency noise is entered.
OFP
XIN_NF
HF Noise Observer
HF Noise Canceller
Mux
0S
Internal OSC
en
CLK Changer
1 S
INT_CLK
0
FINTERNAL
ONP OFP
en
LF Noise Observer
CLK_CHG
ONP IN4(2)MCLK(XO)
o/f
ONPb = 0 LF_on = 1 IN_CLK = 0 High Frq. Noise
INT_CLK 8 periods (250ns x 8 =2us) PS10 CK
en
(8-Bit counter)
PS10(INT_CLK/512) 256 periods (250ns x 512 x 256 =33 ms)
OFP
~ ~
XIN XIN_NF INT_CLK reset INT_CLK OFP_EN CHG_END CLK_CHG
~ ~
Noise Cancel
Low Frq. Noise or Oscillation Fail
~ ~
Clock Change Start(XIN to INT_CLK)
~ ~ ~ ~ ~ ~
Clock Change End(INT_CLK to XIN))
~ ~ ~~ ~~ ~~ ~~
fINTERNAL
Figure 21-1 Block Diagram of ONP & OFP and Respective Wave Forms
~ ~
~ ~
98
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
21.2 Oscillation Fail Processor
The oscillation fail processor (OFP) can change the clock source from external to internal oscillator when the oscillation fail occurred. This function could be enabled or disabled by the "OFP" bit of the Device Configuration Area (MASK option for MC80F0704/0708/0804/0808. And this function can recover the external clock source when the external clock is recovered to normal state. IN4(2)MCLK/CLKXO(XO) Option The "IN4MCLK(XO)", "IN2MCLK(XO)" bit of the Device Configuration Area (MASK option for MC80F0704/0708/0804/ 0808 enables the function to operate the device by using the internal oscillator clock in ONP block as system clock. There is no need to connect the X-tal, resonator, RC and R externally. The user only to connect the XIN pin to VDD. After selecting the this option, the period of internal oscillator clock could be checked by XOUT outputting clock divided the internal oscillator clock by 4.
August 18, 2009 Ver 1.02
99
www.DataSheet.in
MC80F0704/0708/0804/0808
22. Device Configuration Area
The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as POR, ONP, CLK option and security bit. This area is not accessible during normal execution but is readable and writable during FLASH program / verify mode. Note: The Configuration Option may not be read exactly when VDD rising time is very slow. It is recommended to adjust the VDD rising time faster than 40ms/V (200ms from 0V to 5V).
Configuration Option Bits
7 ONP
6 5 4 3 2 1 0 OFP LOCK POR R35EN CLK2 CLK1 CLK0
ADDRESS: 20FFH INITIAL VALUE: 00H
Oscillation configuration 000 : IN4MCLK (Internal 4MHz Oscillation & R33/R34 Enable) 001 : IN2MCLK (Internal 2MHz Oscillation & R33/R34 Enable) 010 : EXRC (External R/RC Oscillation & R34 Enable) 011 : X-tal (Crystal or Resonator Oscillation) 100 : IN4MCLKXO (internal 4MHz Oscillation & R33 Enable & XOUT = fSYS / 4) 101 : IN2MCLKXO (internal 2MHz Oscillation & R33 Enable & XOUT = fSYS / 4) 110 : EXRCXO (External R/RC Oscillation & XOUT = fSYS / 4) 111 : Prohibited RESET/R35 Port configuration 0 : R35 Port Disable (Use RESET) 1 : R35 Port Enable (Disable RESET) POR Use 0 : Disable POR Reset 1 : Enable POR Reset Security Bit 0 : Enable reading User Code 1 : Disable reading User Code OFP use 0 : Disable OFP (Clock Changer) 1 : Enable OFP (Clock Changer) ONP disable 0 : Enable ONP (Enable OFP, Internal 4MHz/2MHz oscillation) 1 : Disable ONP (Disable OFP, Internal 4MHz/2MHz oscillation)
Figure 22-1 Device Configuration Area
100
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
23. Emulator EVA. Board Setting

August 18, 2009 Ver 1.02
101
www.DataSheet.in
MC80F0704/0708/0804/0808
DIP Switch and VR Setting
Before execute the user program, keep in your mind the below DIP S/W Description
configuration

ON/OFF Setting For the MC80F0224/MC80F0448 For the MC80F0708/0808. Must be OFF position.
This connector is only used for a device over 32 PIN. This connector is only used for a device under 32 PIN.
1
ON
Eva. select switch
ON : For the MC80F0224/MC80F0448. OFF : For the MC80F0708/0808.
ON
OFF ON
Use User's AVDD
2 3
These switches select the AVDD source. ON & OFF : Use Eva. VDD OFF & ON : Use User AVDD Normally OFF. EVA. chip can be reset by external user target board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit
OFF
Use Eva. VDD
SW2
AVDD pin select switch
4
This switch select the /Reset source.
5
This switch select the Xout signal on/off.
This switch select Eva. B/D Power supply source.
MDS
SW3
MDS
1
USER Use MDS Power USER Use User's Power
Normally MDS. This switch select Eva. B/D Power supply source.
SW4
1 2
This switch select the R22 or SXOUT. This switch select the R21 or SXIN.
These switchs select the Normal I/O port(off) or Sub-Clock (on). It is reserved for the MC80F0448. ON : SXOUT, SXIN OFF : R22, R21 Don't care (MC80F0224/MC80F0448).
102
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
DIP S/W
Description 1 2 3 4 5 6 These switches select the R33 or XIN These switches select the R34 or XOUT These switches select the R35 or /Reset This is External oscillation socket(CAN Type. OSC)
ON/OFF Setting This switch select the Normal I/O port (on&off) or special function select(off&on). It is reserved for the MC80F0708/0808. ON & OFF : R33,R34,R35 Port selected. OFF & ON : XOUT, XIN , /Reset selected. Don't care (MC80F0224/MC80F0448). This is for External Clock (CAN Type. OSC).
SW5
-
August 18, 2009 Ver 1.02
103
www.DataSheet.in
MC80F0704/0708/0804/0808
104
August 18, 2009 Ver 1.02
www.DataSheet.in
APPENDIX
www.DataSheet.in
MC80F0704/0708/0804/0808
A. INSTRUCTION
A.1 Terminology List
Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
0 Bit Position
Description
Upper Nibble Expression in Opcode
y - x / ()
1 Bit Position
Upper Nibble Expression in Opcode
Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal
~ =
ii
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
A.2 Instruction Map
LOW 00000 00 HIGH 000 001 010 011 100 101 110 111 CLRC CLRG DI CLRV SETC SETG EI 00001 01 SET1 dp.bit " " " " " " " 00010 02 00011 03 00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm 00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp 00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X 00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs 01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA TAX 01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp 01010 0A TCALL 0 01011 0B SETA1 .bit 01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp 01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y 01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP TSPX XCN XAX 01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS (N/A) STOP
BBS BBS A.bit,rel dp.bit,rel " " " " " " " " " " " " " "
TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B
TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit
LOW 10000 HIGH 10 000 001 010 011 100 101 110 111 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1 dp.bit " " " " " " "
10010 12
10011 13
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs MUL DBNE Y DIV XMA {X} LDA {X}+ STA {X}+
11100 1C BIT !abs TEST !abs
11101 1D ADDW dp SUBW dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y XAY XYX
11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI TAY TYA DAA (N/A) NOP
BBC BBC A.bit,rel dp.bit,rel " " " " " " " " " " " " " "
TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp
August 18, 2009 Ver 1.02
iii
www.DataSheet.in
MC80F0704/0708/0804/0808
A.3 Instruction Set
Arithmetic / Logic Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNEMONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DIV OP CODE 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C A8 A9 B9 B8 AF BE 9B BYTE NO 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 2 2 3 1 1 1 CYCLE NO 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 2 4 5 5 2 2 12 Divide : YA / X Q: A, R: Y NV--H-ZDecrement M (M)-1 N-----ZCompare X contents with memory contents (X)-(M) N-----ZC Compare accumulator contents with memory contents (A) -(M) N-----ZC Arithmetic shift left
C 7 6 5 4 3 2 1 0 "0"
OPERATION
FLAG NVGBHIZC
Add with carry. A(A)+(M)+C
NV--H-ZC
Logical AND A (A)(M)
N-----Z-
N-----ZC
Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Unsupported Unsupported
N-----ZC N-----Z-
iv
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
MNEMONIC EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
OP CODE A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
BYTE NO 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
CYCLE NO 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Subtract with carry Logical OR A (A)(M)
"0"
OPERATION
FLAG NVGBHIZC
Exclusive OR A (A)(M)
N-----Z-
Increment M (M)+1
N-----Z-
Logical shift right
7 6 5 4 3 2 1 0 C
N-----ZC
Multiply : YA Y x A
N-----Z-
N-----Z-
Rotate left through carry
C 7 6 5 4 3 2 1 0
N-----ZC
Rotate right through carry
7 6 5 4 3 2 1 0 C
N-----ZC
A ( A ) - ( M ) - ~( C )
NV--HZC
Test memory contents for negative or zero ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0
N-----ZN-----Z-
August 18, 2009 Ver 1.02
v
www.DataSheet.in
MC80F0704/0708/0804/0808
Register / Memory Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNEMONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE BYTE NO 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 CYCLE NO 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Exchange X-register contents with Y-register : X Y -------X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A N-----Z-------Store accumulator contents in memory (M)A -------Load Y-register Y(M) N-----ZLoad X-register X (M) N-----ZX- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm -------Load accumulator A(M) N-----ZOPERATION FLAG NVGBHIZC
-------N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z---------------
vi
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
16-BIT Operation
NO. 1 2 3 4 5 6 7 MNEMONIC ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp OP CODE 1D 5D BD 9D 7D DD 3D BYTE NO 2 2 2 2 2 2 2 CYCLE NO 5 4 6 6 5 5 5 OPERATION 16-Bits add without carry YA ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits substact without carry YA ( YA ) - ( dp +1) ( dp) (YA) - FLAG NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
Bit Manipulation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNEMONIC AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs OP CODE 8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C BYTE NO 3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 CYCLE NO 4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 OPERATION Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A) FLAG NVGBHIZC -------C -------C MM----Z---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
August 18, 2009 Ver 1.02
vii
www.DataSheet.in
MC80F0704/0708/0804/0808
Branch / Jump Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNEMONIC BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage OP CODE y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F BYTE NO 2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2 CYCLE NO 4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 OPERATION Branch if bit clear : if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if minus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H) FLAG NVGBHIZC ------------------------------------------------------------------------------
--------
---------------
--------
--------
24
TCALL n
nA
1
8
--------
viii
August 18, 2009 Ver 1.02
www.DataSheet.in
MC80F0704/0708/0804/0808
Control Operation & Etc.
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI STOP MNEMONIC OP CODE 0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F 7F EF BYTE NO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CYCLE NO 8 3 3 2 4 4 4 4 4 4 4 4 5 6 3 OPERATION Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pcL ( 0FFDEH ) , pcH ( 0FFDFH) . Disable interrupts : I "0" Enable interrupts : I "1" No operation sp sp + 1, sp sp + 1, sp sp + 1, sp sp + 1, A M( sp ) X M( sp ) Y M( sp ) PSW M( sp ) FLAG NVGBHIZC ---1-0------0------1---------------restored
M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator )
--------
-------restored --------
August 18, 2009 Ver 1.02
ix
www.DataSheet.in
MC80F0704/0708/0804/0808
x
August 18, 2009 Ver 1.02
www.DataSheet.in

▲Up To Search▲

Price & Availability of MC80F0704

	To Download MC80F0704 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .